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ICCAD
1994
IEEE
74views Hardware» more  ICCAD 1994»
14 years 2 months ago
Non-scan design-for-testability of RT-level data paths
- This paper presents a non-scan design-for-testability technique applicable to register-transfer(RT) level data path circuits, which are usually very hard-to-test due to the prese...
Sujit Dey, Miodrag Potkonjak
ICCAD
1994
IEEE
115views Hardware» more  ICCAD 1994»
14 years 2 months ago
Fast transient power and noise estimation for VLSI circuits
Abstract - Today's digital design systems are running out of steam, when it comes to meeting the challenges presented by simultaneous switching, power consumption and reliabil...
Wolfgang T. Eisenmann, Helmut E. Graeb
ICCAD
1994
IEEE
104views Hardware» more  ICCAD 1994»
14 years 2 months ago
Module selection and data format conversion for cost-optimal DSP synthesis
In high level synthesis each node of a synchronous dataflow graph (DFG) is scheduled to a specific time and allocated to a processor. In this paper we present new integer linear p...
Kazuhito Ito, Lori E. Lucke, Keshab K. Parhi
ICCD
1994
IEEE
85views Hardware» more  ICCD 1994»
14 years 2 months ago
A Superassociative Tagged Cache Coherence Directory
Dynamically tagged directories are memory-efficient mechanisms for maintaining cache coherence in sharedmemory multiprocessors. These directories use specialpurpose caches of poin...
David J. Lilja, Shanthi Ambalavanan
ICRA
1994
IEEE
111views Robotics» more  ICRA 1994»
14 years 2 months ago
From Spider Robots to Half Disk Robots
We study the problem of computing the set F of accessible and stable placements of a spider robot. The body of this robot is a single point and the legs are line segments attached...
Jean-Daniel Boissonnat, Olivier Devillers, Sylvain...