240 search results - page 13 / 48 » vlsi 2005 |
ISVLSI
2005
IEEE
14 years 1 months ago
2005
IEEE
This paper presents an approach to dynamically balance the pipeline by scaling the stage supply voltages. Simulation results show that by such an approach about 50% improvement in...
ISVLSI
2005
IEEE
14 years 1 months ago
2005
IEEE
This paper carries out a comparative study on the methods of dicing multi-project wafers (MPW). Our dicing method results in using 40% fewer wafers both for low and high volume pr...
GLVLSI
2005
IEEE
14 years 1 months ago
2005
IEEE
The dependence of the propagation delay of the interlayer 3-D interconnects on the vertical through via location and length is investigated. For a variable vertical through via lo...
DATE
2005
IEEE
14 years 1 months ago
2005
IEEE
In this paper, we present an experimental integrated platform for the research, development and evaluation of new VLSI back-end algorithms and design flows. Interconnect scaling ...
GLVLSI
2005
IEEE
14 years 1 months ago
2005
IEEE
We have presented an optimal on-chip buffer allocation and buffer insertion methodology which uses stochastic models of the architecture. This methodology uses finite buffer s...