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EDBT
2010
ACM
133views Database» more  EDBT 2010»
14 years 4 months ago
FPGAs: a new point in the database design space
In line with the insight that “one size” of databases will not fit all application needs [19], the database community is currently exploring various alternatives to commodity...
René Müller, Jens Teubner
GLVLSI
2010
IEEE
187views VLSI» more  GLVLSI 2010»
14 years 2 months ago
Write activity reduction on flash main memory via smart victim cache
Flash Memory is a desirable candidate for main memory replacement in embedded systems due to its low leakage power consumption, higher density and non-volatility characteristics. ...
Liang Shi, Chun Jason Xue, Jingtong Hu, Wei-Che Ts...
ISLPED
2010
ACM
206views Hardware» more  ISLPED 2010»
13 years 10 months ago
Energy efficient implementation of parallel CMOS multipliers with improved compressors
Booth encoding is believed to yield faster multiplier designs with higher energy consumption. 16x16-bit Booth and NonBooth multipliers are analyzed in energy and delay space under...
Dursun Baran, Mustafa Aktan, Vojin G. Oklobdzija
GLVLSI
2010
IEEE
171views VLSI» more  GLVLSI 2010»
14 years 2 months ago
Timing-driven variation-aware nonuniform clock mesh synthesis
Clock skew variations adversely affect timing margins, limiting performance, reducing yield, and may also lead to functional faults. Non-tree clock distribution networks, such as ...
Ameer Abdelhadi, Ran Ginosar, Avinoam Kolodny, Eby...
GLVLSI
2010
IEEE
210views VLSI» more  GLVLSI 2010»
14 years 2 months ago
Overscaling-friendly timing speculation architectures
Processors have traditionally been designed for the worst-case, resulting in designs that have high yields, but are expensive in terms of area and power. Better-than-worst-case (B...
John Sartori, Rakesh Kumar