CN4011A is IEEE 1394a_2000 standard Compliant Physical Layer ASIC. It is a 0.18um mixed-signal ASIC incorporating three analog ports, PLL, reference generator for analog along wit...
We consider the problem of timing analysis in the presence of known false paths. The main difficulty in adaptation of classical breadth-first search to the problem is that at each...
A methodology for reducing ground bounce in typical microprocessors and image processing architectures has been described. As we approach Gigascale Integration, chip power consump...
Mondira Deb Pant, Pankaj Pant, D. Scott Wills, Viv...
Diagnosis algorithms targeting design errors in RTL circuit descriptions are presented in this paper. The algorithms presented exploit the hierarchy available in RTL designs to lo...
The action systems framework has recently been applied to the area of synchronous VLSI design. In this paper, we present a set of concepts necessary in the formal design of synchr...