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ICCD
2007
IEEE
125views Hardware» more  ICCD 2007»
14 years 4 months ago
Low-cost run-time diagnosis of hard delay faults in the functional units of a microprocessor
This paper addresses the run-time diagnosis of delay faults in functional units of microprocessors. Despite the popularity of the stuck-at fault model, it is no longer the only re...
Sule Ozev, Daniel J. Sorin, Mahmut Yilmaz
APCSAC
2006
IEEE
14 years 1 months ago
Functional Unit Chaining: A Runtime Adaptive Architecture for Reducing Bypass Delays
Abstract. Bypass delays are expected to grow beyond 1ns as technology scales. These delays necessitate pipelining of bypass paths at processor frequencies above 1GHz and thus affe...
Lih Wen Koh, Oliver Diessel
GLVLSI
2010
IEEE
156views VLSI» more  GLVLSI 2010»
14 years 24 days ago
A multi-level approach to reduce the impact of NBTI on processor functional units
NBTI is one of the most important silicon reliability problems facing processor designers today. The impact of NBTI can be mitigated at both the circuit and microarchitecture leve...
Taniya Siddiqua, Sudhanva Gurumurthi
ASPDAC
2005
ACM
146views Hardware» more  ASPDAC 2005»
13 years 9 months ago
High-level synthesis for DSP applications using heterogeneous functional units
Abstract— This paper addresses high level synthesis for realtime digital signal processing (DSP) architectures using heterogeneous functional units (FUs). For such special purpos...
Zili Shao, Qingfeng Zhuge, Chun Xue, Bin Xiao, Edw...
VISSYM
2007
13 years 10 months ago
Functional Unit Maps for Data-Driven Visualization of High-Density EEG Coherence
Synchronous electrical activity in different brain regions is generally assumed to imply functional relationships between these regions. A measure for this synchrony is electroenc...
Michael ten Caat, Natasha M. Maurits, Jos B. T. M....