HPCA
2009
IEEE
14 years 12 months ago
2009
IEEE
The verification of an execution against memory consistency is known to be NP-hard. This paper proposes a novel fast memory consistency verification method by identifying a new na...
HPCA
2009
IEEE
14 years 12 months ago
2009
IEEE
The benefits of Out of Order (OOO) processing are well known, as is the effectiveness of predicated execution for unpredictable control flow. However, as previous research has dem...
HPCA
2009
IEEE
14 years 12 months ago
2009
IEEE
Fine-grained dynamic voltage/frequency scaling (DVFS) is an important tool in managing the balance between power and performance in chip-multiprocessors. Although manufacturing pr...
HPCA
2009
IEEE
14 years 12 months ago
2009
IEEE
As the last-level on-chip caches in chip-multiprocessors increase in size, the physical locality of on-chip data becomes important for delivering high performance. The non-uniform...
HPCA
2009
IEEE
14 years 12 months ago
2009
IEEE
Cache hierarchies in future many-core processors are expected to grow in size and contribute a large fraction of overall processor power and performance. In this paper, we postula...
HPCA
2009
IEEE
14 years 12 months ago
2009
IEEE
The Architectural Vulnerability Factor (AVF) of a hardware structure is the probability that a fault in the structure will affect the output of a program. AVF captures both microa...
HPCA
2009
IEEE
14 years 12 months ago
2009
IEEE
Analytical modeling is an alternative to detailed performance simulation with the potential to shorten the development cycle and provide additional insights. This paper proposes a...
HPCA
2009
IEEE
14 years 12 months ago
2009
IEEE
Several recent processor designs have proposed to enhance performance by increasing the clock frequency to the point where timing faults occur, and by adding error-correcting supp...
HPCA
2009
IEEE
14 years 12 months ago
2009
IEEE
Decreasing hardware reliability is expected to impede the exploitation of increasing integration projected by Moore's Law. There is much ongoing research on efficient fault t...
HPCA
2009
IEEE
14 years 12 months ago
2009
IEEE
Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...