The increasing size and complexity of designs is making the use of hardware description languages (HDLs), such as Verilog and VHDL, more prevalent. They are able to describe both ...
This paper describes a two-state methodology for register transfer level (RTL) logic simulation in which the use of the Xstate is completely eliminated inside ASIC designs. Exampl...
At present there are two common types of integrated circuit inductor simulation tools. The first type is based on the Greenhouse methods[1], and obtains a solution in a fraction o...
N. R. Belk, M. R. Frei, M. Tsai, A. J. Becker, K. ...
IC inductance extraction generally produces either port inductances based on simplified current path assumptions or a complete partial inductance matrix. Combining either of thes...
Buffer insertion has become a critical step in deep submicron design, and several buffer insertion/sizing algorithms have been proposed in the literature. However, most of these m...
Charles J. Alpert, Anirudh Devgan, Stephen T. Quay
This work presents an overview of the principles that underlie the speed-up achievable by dynamic hardware reconfiguration, proposes a more precise taxonomy for the execution mode...
Abstract We describe the use of parametric representations of Boolean predicates to encode data-space constraints and signi cantly extend the capacity of formal veri cation. The co...
Mark Aagaard, Robert B. Jones, Carl-Johan H. Seger