Sciweavers

DAC
2000
ACM
14 years 3 months ago
Modeling and simulation of real defects using fuzzy logic
Real defects (e.g. stuck-at or bridging faults) in the VLSI circuits cause intermediate voltages and can not be modeled as ideal shorts. In this paper we first show that the trad...
Amir Attarha, Mehrdad Nourani, Caro Lucas
DAC
2000
ACM
14 years 3 months ago
TACO: timing analysis with coupling
: The impact of coupling capacitance on delay is usually estimated by scaling the coupling capacitances (often by a factor of 2) and modeling them as grounded. This simple approach...
Ravishankar Arunachalam, Karthik Rajagopal, Lawren...
CAMP
2000
IEEE
14 years 4 months ago
A Distributed Architecture for Autonomous Navigation of Robots
The paper shows a distributed architecture for autonomous robot navigation. The architecture is based on three modules that are implemented on separate and interacting agents: the...
Vito Di Gesù, B. Lenzitti, Giosuè Lo...
CAMP
2000
IEEE
14 years 4 months ago
Homography Based Parallel Volume Intersection: Toward Real-Time Volume Reconstruction using Active Cameras
Silhouette volume intersection is one of the most popular ideas for reconstructing the 3D volume of an object from multi-viewpoint silhouette images. This paper presents a novel p...
Toshikazu Wada, Xiaojun Wu, Shogo Tokai, Takashi M...
CAMP
2000
IEEE
14 years 4 months ago
An FPGA Architecture for High Speed Edge and Corner Detection
This paper presents an FPGA based architecture for high speed edge and corner detection. Applications targeted are in high speed computer vision (i.e. more than 100 images per sec...
Cesar Torres-Huitzil, Miguel Arias-Estrada
APCSAC
2000
IEEE
14 years 4 months ago
Cost/Performance Tradeoff of n-Select Square Root Implementations
Hardware square-root units require large numbers of gates even for iterative implementations. In this paper, we present four low-cost high-performance fullypipelined n-select impl...
Wanming Chu, Yamin Li
APCSAC
2000
IEEE
14 years 4 months ago
Micro-Threading: A New Approach to Future RISC
This paper briefly reviews the current research into RISC microprocessor architecture, which now seems to be so complex as to make the acronym somewhat of an oxymoron. In response...
Chris R. Jesshope, Bing Luo
DAC
2003
ACM
14 years 4 months ago
Efficient compression and application of deterministic patterns in a logic BIST architecture
We present a novel method to efficiently generate, compress and apply test patterns in a logic BIST architecture. Patterns are generated by a modified automatic test pattern gener...
Peter Wohl, John A. Waicukauski, Sanjay Patel, Min...