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HPCA
1999
IEEE
14 years 3 days ago
The Synergy of Multithreading and Access/Execute Decoupling
This work presents and evaluates a novel processor microarchitecture which combines two paradigms: access/ execute decoupling and simultaneous multithreading. We investigate how b...
Joan-Manuel Parcerisa, Antonio González
HPCA
1999
IEEE
14 years 3 days ago
Using Lamport Clocks to Reason about Relaxed Memory Models
Cache coherence protocols of current shared-memory multiprocessors are difficult to verify. Our previous work proposed an extension of Lamport's logical clocks for showing th...
Anne Condon, Mark D. Hill, Manoj Plakal, Daniel J....
HPCA
1999
IEEE
14 years 3 days ago
Access Order and Effective Bandwidth for Streams on a Direct Rambus Memory
Processor speeds are increasing rapidly, and memory speeds are not keeping up. Streaming computations (such as multi-media or scientific applications) are among those whose perfor...
Sung I. Hong, Sally A. McKee, Maximo H. Salinas, R...
HPCA
1999
IEEE
14 years 3 days ago
Impulse: Building a Smarter Memory Controller
Impulse is a new memory system architecture that adds two important features to a traditional memory controller. First, Impulse supports application-specific optimizations through...
John B. Carter, Wilson C. Hsieh, Leigh Stoller, Ma...
HPCA
1999
IEEE
14 years 3 days ago
WildFire: A Scalable Path for SMPs
Researchers have searched for scalable alternatives to the symmetric multiprocessor (SMP) architecture since it was first introduced in 1982. This paper introduces an alternative ...
Erik Hagersten, Michael Koster
HPCA
1999
IEEE
14 years 3 days ago
Dynamically Exploiting Narrow Width Operands to Improve Processor Power and Performance
In general-purpose microprocessors, recent trends have pushed towards 64-bit word widths, primarily to accommodate the large addressing needs of some programs. Many integer proble...
David Brooks, Margaret Martonosi
HPCA
1999
IEEE
14 years 3 days ago
Limits to the Performance of Software Shared Memory: A Layered Approach
Much research has been done in fast communication on clusters and in protocols for supporting software shared memory across them. However, the end performance of applications that...
Angelos Bilas, Dongming Jiang, Yuanyuan Zhou, Jasw...
HPCA
1999
IEEE
14 years 3 days ago
Comparative Evaluation of Fine- and Coarse-Grain Approaches for Software Distributed Shared Memory
Symmetric multiprocessors (SMPs) connected with low-latency networks provide attractive building blocks for software distributed shared memory systems. Two distinct approaches hav...
Sandhya Dwarkadas, Kourosh Gharachorloo, Leonidas ...
HPCA
1999
IEEE
14 years 3 days ago
Improving the Accuracy vs. Speed Tradeoff for Simulating Shared-Memory Multiprocessors with ILP Processors
Previous simulators for shared-memory architectures have imposed a large tradeoff between simulation accuracy and speed. Most such simulators model simple processors that do not e...
Murthy Durbhakula, Vijay S. Pai, Sarita V. Adve