ASAP
2007
IEEE
14 years 1 months ago
2007
IEEE
This paper presents the enhancement of an ASIP’s floating point performance by coupling of a co-processor and adding of special instructions. Processor hardware modifications an...
ASAP
2007
IEEE
14 years 1 months ago
2007
IEEE
Network processors utilizing general-purpose instruction-set architectures (ISA) limit network throughput due to latency incurred from cryptography and hashing applications (AES, ...
ASAP
2007
IEEE
14 years 1 months ago
2007
IEEE
This paper explores the reliability of three different minimum fan-in majority gates full adder (FA) designs, and compares them to the performance of a standard XOR-based FA. The ...
ASAP
2007
IEEE
14 years 1 months ago
2007
IEEE
Interconnect validation is an important early step toward global SoC (System-On-Chip) validation. Fast performances evaluation and design space exploration for NoCs (Networks-On-C...
ASAP
2007
IEEE
14 years 1 months ago
2007
IEEE
ASAP
2007
IEEE
14 years 1 months ago
2007
IEEE
In high-level synthesis, as for compilers, an important question is when register assignment should take place. Unlike compilers for which the processor architecture is given, syn...
ASAP
2007
IEEE
14 years 1 months ago
2007
IEEE
Abstract— The problem of calculating accurate dose distributions lies in the heart of modern radiation therapy for cancer treatment. Software implementations of dose calculation ...
ASAP
2007
IEEE
14 years 1 months ago
2007
IEEE
FPGA (Field Programmable Gate Array) based reconfigurable processor has been shown to meet the increasingly challenging performance targets and shorter time-to-market pressures. I...
ASAP
2007
IEEE
14 years 1 months ago
2007
IEEE
A novel object-oriented processor is proposed in this paper, which provides support for object addressing, message passing and dynamic memory management. Object running on this pr...
ASAP
2007
IEEE
14 years 1 months ago
2007
IEEE
This paper presents an optimized design approach of two’s complement large-size squarers using embedded multipliers in FPGAs. The realization is based on BaughWooley’s algorit...