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ARC
2008
Springer
115views Hardware» more  ARC 2008»
14 years 1 months ago
A High Throughput FPGA-based Floating Point Conjugate Gradient Implementation
As Field Programmable Gate Arrays (FPGAs) have reached capacities beyond millions of equivalent gates, it becomes possible to accelerate floating-point scientific computing applica...
Antonio Roldao Lopes, George A. Constantinides
ARC
2008
Springer
87views Hardware» more  ARC 2008»
14 years 1 months ago
Online Hardware Task Scheduling and Placement Algorithm on Partially Reconfigurable Devices
In this paper, we propose an online hardware task scheduling and placement algorithm and evaluate it performance. Experimental results on large random task set show that our algori...
Thomas Marconi, Yi Lu 0004, Koen Bertels, Georgi G...
ARC
2008
Springer
126views Hardware» more  ARC 2008»
14 years 1 months ago
DNA Physical Mapping on a Reconfigurable Platform
Reconfigurable architectures enable the hardware function to be implemented by the user and, due to its characteristics, have been used in many areas, including Bioinformatics. One...
Adriano Idalgo, Nahri Moreano
ARC
2008
Springer
112views Hardware» more  ARC 2008»
14 years 1 months ago
Optimal Unroll Factor for Reconfigurable Architectures
Abstract. Loops are an important source of optimization. In this paper, we address such optimizations for those cases when loops contain kernels mapped on reconfigurable fabric. We...
Ozana Silvia Dragomir, Elena Moscu Panainte, Koen ...
ARC
2008
Springer
175views Hardware» more  ARC 2008»
14 years 1 months ago
Multivariate Gaussian Random Number Generator Targeting Specific Resource Utilization in an FPGA
Abstract. Financial applications are one of many fields where a multivariate Gaussian random number generator plays a key role in performing computationally extensive simulations. ...
Chalermpol Saiprasert, Christos-Savvas Bouganis, G...
ARC
2008
Springer
104views Hardware» more  ARC 2008»
14 years 1 months ago
PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive Applications
Abstract. In this paper, we present the PARO design tool for the automated hardware synthesis of massively parallel embedded architectures for given dataflow dominant applications....
Frank Hannig, Holger Ruckdeschel, Hritam Dutta, J&...
ARC
2008
Springer
141views Hardware» more  ARC 2008»
14 years 1 months ago
A Parallel Hardware Architecture for Image Feature Detection
Abstract. This paper presents a real time parallel hardware architecture for image feature detection based on the SIFT (Scale Invariant Feature Transform) algorithm. This architect...
Vanderlei Bonato, Eduardo Marques, George A. Const...
ARC
2008
Springer
112views Hardware» more  ARC 2008»
14 years 1 months ago
Lossless Compression for Space Imagery in a Dynamically Reconfigurable Architecture
Abstract. This paper presents a novel dynamically reconfigurable hardware architecture for lossless compression and its optimization for space imagery. The proposed system makes us...
Xiaolin Chen, Cedric Nishan Canagarajah, Raffaele ...
ARC
2008
Springer
186views Hardware» more  ARC 2008»
14 years 1 months ago
FPGA-based Real-time Super-Resolution on an Adaptive Image Sensor
Recent technological advances in imaging industry have lead to the production of imaging systems with high density pixel sensors. However, their long exposure times limit their app...
Maria E. Angelopoulou, Christos-Savvas Bouganis, P...