A virtual 3-D extractor of the single dielectric is presented in this paper. In the indirect boundary integral equations, the plane charge distribution on the surface of conductors...
Abstract--We present a processor-programmable built-in selftest (BIST) scheme suitable for embedded memory testing in the system-on-a-chip (SOC) environment. The proposed BIST circ...
ct,. In this paper we study the delay associated with transmission of data through busses. Previous work in this area has presented models for delay assuming a distributed wire mqd...
Asynchronous, self-timed, logic is often eschewed in digital design because of its ad-hoc methodologies and lack of available design tools. This paper describes a complete High Le...
Power-efficient design requires reducing power dissipation in all parts of the design and during all stages of the design process subject to constraints on the system performance ...
Abstract-- We are proposing "PPRAM-Link": a new highspeed communication standard for merged-DRAM/logic SoC architecture. PPRAM-Link standard is composed of physical/logic...