ICCAD
2009
IEEE
13 years 9 months ago
2009
IEEE
Double patterning technology (DPT) has emerged as the most hopeful candidate for the next technology node of the ITRS roadmap [1]. The goal of a DPT decomposer is to decompose the...
ICCAD
2009
IEEE
2009
IEEE
An efficient wakeup scheduling considering resource constraint for sensor-based power gating designs
13 years 9 months ago
Power gating has been a very effective way to reduce leakage power. One important design issue for a power gating design is to limit the surge current during the wakeup process. N...
ICCAD
2009
IEEE
13 years 9 months ago
2009
IEEE
The emerging Spin Torque Transfer memory (STT-RAM) is a promising candidate for future on-chip caches due to STT-RAM's high density, low leakage, long endurance and high acce...
ICCAD
2009
IEEE
13 years 9 months ago
2009
IEEE
Clock skew scheduling has been effectively used to reduce the clock period of sequential circuits. However, this technique may become impractical if a different skew must be appli...
ICCAD
2009
IEEE
13 years 9 months ago
2009
IEEE
While Dynamic Voltage Scaling (DVS) remains as a popular energy management technique for real-time embedded applications, recent research has identified significant and negative i...
ICCAD
2009
IEEE
13 years 9 months ago
2009
IEEE
The lack of good "correlation" between pre-silicon simulated delays and measured delays on silicon (silicon data) has spurred efforts on so-called silicon debug. The ide...
ICCAD
2009
IEEE
13 years 9 months ago
2009
IEEE
The flip-chip package is introduced for modern IC designs with higher integration density and larger I/O counts. In this paper, we consider the pre-assignment flip-chip routing pr...
ICCAD
2009
IEEE
13 years 9 months ago
2009
IEEE
This paper accurately considers wire short defects and proposes an algorithm to guarantee IC chip yield rate improvement for redundant wire insertion. Without considering yield ra...
ICCAD
2009
IEEE
13 years 9 months ago
2009
IEEE
ICCAD
2009
IEEE
13 years 9 months ago
2009
IEEE
Boolean satisfiability (SAT) based methods have traditionally been popular for formally verifying properties for digital circuits. We present a novel methodology for formulating a...