This paper presents a testability improvement method for digital systems described in VHDL behavioral specification. The method is based on testability analysis at registertransfe...
Cyclic corrector codes, or "block codes", are often used in telecommunications systems. To facilitate the design of coding/decoding circuits using this type of code, we ...
We present a rigorous but transparent semantic de nition of VHDL'93 covering the complete signal behavior and time model including the various wait statements and signal assi...
This paper presents an algorithm for generation of test patterns for strong robust path delay faults, i.e. tests that propagate the fault along a single path and additionally are ...
System-levelpartitioning assigns functionalobjects such as tasks or code segments to system-level components such as o-the-shelf processors or application-specic architectures in...
This paper describes a unique approach to scheduling and allocation problem in high-level synthesis using genetic algorithm (GA). This approach is dierent from a previous attempt ...
developed and standardised, for example CAN[1][2], J1850[3]. THE ELECTRONIC VEHICLE TODAYVHDL has been used to develop a simulator for automotive databus networks. This is a design...
This paper describes two approaches to the automatic generation of behavioral VHDL models from descriptions written in natural language. Both approaches are based on a modeling st...
Walling R. Cyre, Jim Armstrong, M. Manek-Honcharik...
Abstract -- A general framework for synthesis of asynchronous control circuits at the state graph level is proposed. The framework can consider both concurrency reduction as well a...
Bill Lin, Chantal Ykman-Couvreur, Peter Vanbekberg...