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15

GLVLSI
1998
IEEE

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A Self Timed Asynchronous Router for an Heterogeneous Parallel Machine

14 years 3 months ago

A Self Timed Asynchronous Router for an Heterogeneous Parallel Machine

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Eric Senn, Bertrand Zavidovique

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20

GLVLSI
1998
IEEE

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A Design-for-Testability Technique for Detecting Delay Faults in Logic Circuits

14 years 3 months ago

A Design-for-Testability Technique for Detecting Delay Faults in Logic Circuits

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Kaamran Raahemifar, Majid Ahmadi

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32

GLVLSI
1998
IEEE

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Test Compaction for Synchronous Sequential Circuits by Test Sequence Recycling

14 years 3 months ago

Test Compaction for Synchronous Sequential Circuits by Test Sequence Recycling

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Irith Pomeranz, Sudhakar M. Reddy

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27

GLVLSI
1998
IEEE

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Design of Clock Distribution Networks in Presence of Process Variations

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Design of Clock Distribution Networks in Presence of Process Variations

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Mohamed Nekili, Yvon Savaria, Guy Bois

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20

GLVLSI
1998
IEEE

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MDG-based Verification by Retiming and Combinational Transformations

14 years 3 months ago

MDG-based Verification by Retiming and Combinational Transformations

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Otmane Aït Mohamed, Eduard Cerny, Xiaoyu Song

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23

GLVLSI
1998
IEEE

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A Quantitative Study of the Benefits of Area-I/O in FPGAs

14 years 3 months ago

A Quantitative Study of the Benefits of Area-I/O in FPGAs

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Herwig Van Marck, Jo Depreitere, Dirk Stroobandt, ...

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23

GLVLSI
1998
IEEE

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The Chinese Abacus Method: Can We Use It for Digital Arithmetic?

14 years 3 months ago

The Chinese Abacus Method: Can We Use It for Digital Arithmetic?

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Franco Maloberti, Chen Gang

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29

GLVLSI
1998
IEEE

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A Methodology for High Level Power Estimation and Exploration

14 years 3 months ago

A Methodology for High Level Power Estimation and Exploration

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Vamsi Krishna, N. Ranganathan

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21

GLVLSI
1998
IEEE

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Practical Approaches to the Automatic Verification of an ATM Switch Fabric Using VIS

14 years 3 months ago

Practical Approaches to the Automatic Verification of an ATM Switch Fabric Using VIS

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Jianping Lu, Sofiène Tahar

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27

GLVLSI
1998
IEEE

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Effective Capacitance Macro-Modelling for Architectural-Level Power Estimation

14 years 3 months ago

Effective Capacitance Macro-Modelling for Architectural-Level Power Estimation

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Muhammad M. Khellah, Mohamed I. Elmasry

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