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    VLSID
    1999
    IEEE
    97views VLSI» more  VLSID 1999»
    A New Methodology for Concurrent Technology Development and Cell Library Optimization
    13 years 11 months ago
    A New Methodology for Concurrent Technology Development and Cell Library Optimization
    Download  www.pdf.com
    To minimize the time to market and cost of new sub 0.25um process technologies and products, PDF Solutions, Inc., has developed a new comprehensive approach based on the use of pr...
    Marko P. Chew, Sharad Saxena, Thomas F. Cobourn, P...
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    VLSID
    1999
    IEEE
    86views VLSI» more  VLSID 1999»
    Multi-Valued Logic Synthesis
    13 years 11 months ago
    Multi-Valued Logic Synthesis
    Download  www.cs.uleth.ca
    We survey some of the methods used for manipulating, representing, and optimizing multi-valued logic with the view of both building a better understanding of the more specialized ...
    Robert K. Brayton, Sunil P. Khatri
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    VLSID
    1999
    IEEE
    102views VLSI» more  VLSID 1999»
    A Low-Power Wireless Camera System
    13 years 11 months ago
    A Low-Power Wireless Camera System
    Download  mtlweb.mit.edu
    This paper describes the system design of a lowpower wireless camera. A system level approach is used to reduce energy dissipation and maximize battery lifetime. System properties...
    Anantha Chandrakasan, Abram P. Dancy, James Goodma...
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    VLSID
    1999
    IEEE
    99views VLSI» more  VLSID 1999»
    Array Index Allocation under Register Constraints in DSP Programs
    13 years 11 months ago
    Array Index Allocation under Register Constraints in DSP Programs
    Download  ls12-www.cs.tu-dortmund.de
    Abstract Code optimization for digital signal processors DSPs has been identi ed as an important new topic in system-level design of embedded systems. Both DSP processors and algor...
    Anupam Basu, Rainer Leupers, Peter Marwedel
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    VLSID
    1999
    IEEE
    87views VLSI» more  VLSID 1999»
    Digital Circuit Design for Minimum Transient Energy and a Linear Programming Method
    13 years 11 months ago
    Digital Circuit Design for Minimum Transient Energy and a Linear Programming Method
    Download  www.eng.auburn.edu
    This paper provides a theoretical basis for eliminating or reducing the energy consumption due to transients in a synchronous digital circuit. The transient energy is minimized wh...
    Vishwani D. Agrawal, Michael L. Bushnell, Ganapath...
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    GLVLSI
    1999
    IEEE
    89views VLSI» more  GLVLSI 1999»
    ICE: Incremental 3-Dimensional Capacitance and Resistance Extraction for an Iterative Design Environment
    13 years 11 months ago
    ICE: Incremental 3-Dimensional Capacitance and Resistance Extraction for an Iterative Design Environment
    Download  www.cecs.uci.edu
    Yanhong Yuan, Prithviraj Banerjee
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    GLVLSI
    1999
    IEEE
    105views VLSI» more  GLVLSI 1999»
    An Integrated Approach for Synthesizing LUT Networks
    13 years 11 months ago
    An Integrated Approach for Synthesizing LUT Networks
    Download  www.kecl.ntt.co.jp
    This paper presents a method for synthesizing lookup table (LUT) networks. The strategy employed by our method is very different from the strategies of previous methods; many deco...
    Shigeru Yamashita, Hiroshi Sawada, Akira Nagoya
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    GLVLSI
    1999
    IEEE
    81views VLSI» more  GLVLSI 1999»
    Parallel Saturating Fractional Arithmetic Units
    13 years 11 months ago
    Parallel Saturating Fractional Arithmetic Units
    Download  mesa.ece.wisc.edu
    This paper describes the designs of a saturating adder, multiplier, single MAC unit, and dual MAC unit with one cycle latencies. The dual MAC unit can perform two saturating MAC o...
    Navindra Yadav, Michael J. Schulte, John Glossner
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    GLVLSI
    1999
    IEEE
    85views VLSI» more  GLVLSI 1999»
    Reducing BDD Size by Exploiting Structural Connectivity
    13 years 11 months ago
    Reducing BDD Size by Exploiting Structural Connectivity
    Download  www.cecs.uci.edu
    Ronnie L. Wright, Michael A. Shanblatt
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    GLVLSI
    1999
    IEEE
    133views VLSI» more  GLVLSI 1999»
    Residue Arithmetic Circuits Based on Signed-Digit Number Representation and the VHDL Implementation
    13 years 11 months ago
    Residue Arithmetic Circuits Based on Signed-Digit Number Representation and the VHDL Implementation
    Download  www.cs.york.ac.uk
    Shugang Wei, Kensuke Shimizu
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