VLSID
1999
IEEE
13 years 11 months ago
1999
IEEE
This paper presents a detailed description of the application of a formal verification methodology to an ARM processor. The processor, a hybrid between the ARM7 and the StrongARM ...
VLSID
1999
IEEE
13 years 11 months ago
1999
IEEE
Retiming is a transformation that optimizes a sequential circuit by relocating the registers. When the circuit has an initial state, one must compute an equivalent initial state f...
VLSID
1999
IEEE
13 years 11 months ago
1999
IEEE
In this paper we address the problem of detailed FPGA routing using Boolean formulation methods. In the context of FPGA routing where routing resources are fixed, Boolean formulat...
VLSID
1999
IEEE
13 years 11 months ago
1999
IEEE
Recently Lillis, et al. presented an elegant dynamic programming approach to RC interconnect delay optimization through driver sizing, repeater insertion, and, wire sizing which e...
VLSID
1999
IEEE
13 years 11 months ago
1999
IEEE
Residue Number System based applications involve modulo-arithmetic which is typically implemented using look-up-tables (LUTs) for a small value of modulus. In this paper, we prese...
VLSID
1999
IEEE
13 years 11 months ago
1999
IEEE
A new approach for CMOS op-amp circuit synthesis has proposed here. The approach is based on the observation that the rst order behavior of a MOS transistor in the saturation regi...
VLSID
1999
IEEE
13 years 11 months ago
1999
IEEE
To reduce manufacturing variation due to chemicalmechanical polishing and to improve yield, layout must be made uniform with respect to density criteria. This is achieved by layou...
VLSID
1999
IEEE
13 years 11 months ago
1999
IEEE
Interconnect tuning and repeater insertion are necessary to optimize interconnectdelay, signalperformanceandintegrity, andinterconnectmanufacturability and reliability. Repeater i...
VLSID
1999
IEEE
13 years 11 months ago
1999
IEEE
We describe an improved iterationless approach for computing the effective capacitance of an interconnect load at a driving gate output. The speed and accuracy of our approach mak...
VLSID
1999
IEEE
13 years 11 months ago
1999
IEEE
Accurate output response computation of RC interconnects under various input excitations is a key issue in deep submicron delay analysis.In this paper,we present an exact analysis...