A New Design for Double Edge Triggered Flip-flops

-- The logic construction of a double-edge-triggered (DET) flip-flop, which can receive input signal at two levels of the clock, is analyzed and a new circuit design of CMOS DET flip-flop is proposed. Simulation using SPICE and a 1 micron technology shows that this DET flip-flop has ideal logic functionality, a simpler structure, lower delay time and higher maximum data rate compared to other existing CMOS DET flipflops. By simulating and comparing the proposed DET flip-flop with the traditional single-edge-triggered (SET) flip-flop, it is shown that the proposed DET flip-flop reduces power dissipation by half while keeping the same date rate.

• Type: Conference
• Year: 1998
• Where: ASPDAC
• Authors: Massoud Pedram, Qing Wu, Xunwei Wu
• Keywords: ASPDAC 1998, CMOS DET Flip-flop, DET Flip-flop, Flip-flop Reduces Power, Hardware