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ASPDAC
2005
ACM
130views Hardware» more  ASPDAC 2005»
14 years 5 months ago
Sequential equivalence checking using cuts
Wei Huang, Pushan Tang, Min Ding
ASPDAC
2005
ACM
127views Hardware» more  ASPDAC 2005»
14 years 5 months ago
Clock network minimization methodology based on incremental placement
: In ultra-deep submicron VLSI circuits, clock network is a major source of power consumption and power supply noise. Therefore, it is very important to minimize clock network size...
Liang Huang, Yici Cai, Qiang Zhou, Xianlong Hong, ...
ASPDAC
2005
ACM
73views Hardware» more  ASPDAC 2005»
14 years 5 months ago
An-OARSMan: obstacle-avoiding routing tree construction with good length performance
- Routing is one of the important steps in VLSI/ULSI physical design. The rectilinear Steiner minimum tree (RSMT) construction is an essential part of routing. Since macro cells, I...
Yu Hu, Tong Jing, Xianlong Hong, Zhe Feng 0002, Xi...
ASPDAC
2005
ACM
95views Hardware» more  ASPDAC 2005»
14 years 5 months ago
Timing analysis considering temporal supply voltage fluctuation
Abstract— This paper proposes an approach to cope with temporal power/ground voltage fluctuation for static timing analysis. The proposed approach replaces temporal noise with a...
Masanori Hashimoto, Junji Yamaguchi, Takashi Sato,...
ASPDAC
2005
ACM
92views Hardware» more  ASPDAC 2005»
14 years 5 months ago
Detailed placement for improved depth of focus and CD control
— Sub-resolution assist features (SRAFs) provide an absolutely essential technique for critical dimension (CD) control and process window enhancement in subwavelength lithography...
Puneet Gupta, Andrew B. Kahng, Chul-Hong Park
ASPDAC
2005
ACM
81views Hardware» more  ASPDAC 2005»
14 years 5 months ago
System-level communication modeling for network-on-chip synthesis
— As we are entering the network-on-chip era and system communication is becoming a dominating factor, comon abstraction and synthesis are becoming the integral part of system de...
Andreas Gerstlauer, Dongwan Shin, Rainer Döme...
ASPDAC
2005
ACM
193views Hardware» more  ASPDAC 2005»
14 years 5 months ago
VLSI on-chip power/ground network optimization considering decap leakage currents
- In today’s power/ground(P/G) network design, on-chip decoupling capacitors(decaps) are usually made of MOS transistors with source and drain connected together. The gate leak...
Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, ...
ASPDAC
2005
ACM
101views Hardware» more  ASPDAC 2005»
14 years 5 months ago
Lower bounds for dynamic BDD reordering
— In this paper we present new lower bounds on BDD size. These lower bounds are derived from more general lower bounds that recently were given in the context of exact BDD minimi...
Rüdiger Ebendt, Rolf Drechsler
ASPDAC
2005
ACM
115views Hardware» more  ASPDAC 2005»
14 years 5 months ago
Low-power domino circuits using NMOS pull-up on off-critical paths
- Domino logic is used extensively in high speed microprocessor datapath design. Although domino gates have small propagation delay, they consume relatively more power. We propose ...
Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhij...
ASPDAC
2005
ACM
86views Hardware» more  ASPDAC 2005»
14 years 5 months ago
Thermal-driven multilevel routing for 3-D ICs
3-D IC has a great potential for improving circuit performance and degree of integration. It is also an attractive platform for system-on-chip or system-in-package solutions. A cr...
Jason Cong, Yan Zhang