Abstract— The sparsification of the reluctance matrix L−1 (where L denotes the usual inductance matrix L) has been widely used in several recent investigations to make the pro...
Hong Li, Venkataramanan Balakrishnan, Cheng-Kok Ko...
Abstract— This paper presents an optimized channel usage between simulator and accelerator when the simulator models transaction-level SoC while accelerator models RTL sub-blocks...
In this paper, we present the power estimation methodologies for the development of a low-power security processor that contains significant amount of logic and memory. For the lo...
As the minimum feature sizes of VLSI circuits get smaller while the clock frequency increases, the effects of process variations become significant. We propose a UST/DME based ap...
— We present SoCExplore, a framework for fast communicationcentric design space exploration of complex SoCs with networkbased interconnects. Speed-up in exploration is achieved t...
New substrate isolation structures using pattern stacked pn junctions for on-chip inductors in standard CMOS technology are presented. For the first time, through increasing the re...
Hongyan Jian, Zhangwen Tang, Jie He, Jinglan He, M...
-- This paper presents a novel global routing algorithm, AT-PO-GR, to minimize the routing area under both congestion, timing, and RLC crosstalk constraints. The proposed algorithm...
— As microprocessor technology continues to scale into the nanometer regime, recent studies show that interconnect delay will be a limiting factor for performance, and multiple c...
Abstract— Frequency dependent interconnect analysis is challenging since lumped equivalent circuit models extracted at different frequencies exhibit distinct time and frequency d...