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    ASPDAC
    2006
    ACM
    143views Hardware» more  ASPDAC 2006»
    Constraint-driven bus matrix synthesis for MPSoC
    14 years 6 months ago
    Constraint-driven bus matrix synthesis for MPSoC
    Download  www.cecs.uci.edu
    – Modern multi-processor system-on-chip (MPSoC) designs have high bandwidth constraints which must be satisfied by the underlying communication architecture. Bus matrix based com...
    Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdha...
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    ASPDAC
    2006
    ACM
    84views Hardware» more  ASPDAC 2006»
    Parasitics extraction involving 3-D conductors based on multi-layered Green's function
    14 years 6 months ago
    Parasitics extraction involving 3-D conductors based on multi-layered Green's function
    Download  www.cecs.uci.edu
    Abstract— An efficient algorithm for three-dimensional (3D) capacitance extraction on multi-layered and lossy substrate is presented. The new algorithm represents a major improv...
    Zuochang Ye, Zhiping Yu
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    ASPDAC
    2006
    ACM
    122views Hardware» more  ASPDAC 2006»
    Reusable component IP design using refinement-based design environment
    14 years 6 months ago
    Reusable component IP design using refinement-based design environment
    Download  www.cecs.uci.edu
    - We propose a method of enhancing the reusability of the component IPs by separating communication and computation for a system function. In this approach, we assume that the comp...
    Sanggyu Park, Sang-yong Yoon, Soo-Ik Chae
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    ASPDAC
    2006
    ACM
    92views Hardware» more  ASPDAC 2006»
    Utility of the OpenAccess database in academic research
    14 years 6 months ago
    Utility of the OpenAccess database in academic research
    Download  www.eecs.umich.edu
    The proliferation of OpenAccess is opening promising new research opportunities to academic communities. The benefits of adopting an OpenAccess based approach to EDA research are...
    David A. Papa, Igor L. Markov, Philip Chong
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    ASPDAC
    2006
    ACM
    116views Hardware» more  ASPDAC 2006»
    Abridged addressing: a low power memory addressing strategy
    14 years 6 months ago
    Abridged addressing: a low power memory addressing strategy
    Download  www.cse.iitd.ernet.in
    Abstract— The memory subsystem is known to comprise a significant fraction of the power dissipation in embedded systems. The memory addressing strategy, which determines the seq...
    Preeti Ranjan Panda
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    ASPDAC
    2006
    ACM
    100views Hardware» more  ASPDAC 2006»
    Generation of shorter sequences for high resolution error diagnosis using sequential SAT
    14 years 6 months ago
    Generation of shorter sequences for high resolution error diagnosis using sequential SAT
    Download  www.cecs.uci.edu
    Commonly used pattern sources in simulation-based verification include random, guided random, or design verification patterns. Although these patterns may help bring the design ...
    Sung-Jui (Song-Ra) Pan, Kwang-Ting Cheng, John Moo...
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    ASPDAC
    2006
    ACM
    84views Hardware» more  ASPDAC 2006»
    Optimal topology exploration for application-specific 3D architectures
    14 years 6 months ago
    Optimal topology exploration for application-specific 3D architectures
    Download  www.aspdac.com
    Ozcan Ozturk, Feng Wang 0004, Mahmut T. Kandemir, ...
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    ASPDAC
    2006
    ACM
    140views Hardware» more  ASPDAC 2006»
    A 52mW 1200MIPS compact DSP for multi-core media SoC
    14 years 6 months ago
    A 52mW 1200MIPS compact DSP for multi-core media SoC
    Download  www.cecs.uci.edu
    - This paper presents a DSP core for multi-core media SoC, which is optimized to execute a set of signal processing tasks very efficiently. The fully-programmable core has a data-c...
    Shih-Hao Ou, Tay-Jyi Lin, Chao-Wei Huang, Yu-Ting ...
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    ASPDAC
    2006
    ACM
    103views Hardware» more  ASPDAC 2006»
    Low area pipelined circuits by multi-clock cycle paths and clock scheduling
    14 years 6 months ago
    Low area pipelined circuits by multi-clock cycle paths and clock scheduling
    Download  www.cecs.uci.edu
    — A new algorithm is proposed to reduce the number of intermediate registers of a pipelined circuit using a combination of multi-clock cycle paths and clock scheduling. The algor...
    Bakhtiar Affendi Rosdi, Atsushi Takahashi
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    ASPDAC
    2006
    ACM
    92views Hardware» more  ASPDAC 2006»
    Double edge triggered Feedback Flip-Flop in sub 100NM technology
    14 years 6 months ago
    Double edge triggered Feedback Flip-Flop in sub 100NM technology
    Download  www.cecs.uci.edu
    In this paper, a new flip-flop called Double-edge triggered Feedback Flip-Flop (DFFF) is proposed. The dynamic power consumption of DFFF is reduced by avoiding unnecessary interna...
    S. H. Rasouli, A. Amirabadi, A. Seyedi, Ali Afzali...
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