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    ASPDAC
    2008
    ACM
    116views Hardware» more  ASPDAC 2008»
    Faster projection based methods for circuit level verification
    14 years 2 months ago
    Faster projection based methods for circuit level verification
    Download  www.cs.ubc.ca
    As VLSI fabrication technology progresses to 65nm feature sizes and smaller, transistors no longer operate as ideal switches. This motivates the verification of digital circuits us...
    Chao Yan, Mark R. Greenstreet
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    ASPDAC
    2008
    ACM
    72views Hardware» more  ASPDAC 2008»
    A capacitive boosted buffer technique for high-speed process-variation-tolerant interconnect in UDVS application
    14 years 2 months ago
    A capacitive boosted buffer technique for high-speed process-variation-tolerant interconnect in UDVS application
    Download  www.cecs.uci.edu
    Saihua Lin, Yu Wang 0002, Rong Luo, Huazhong Yang
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    ASPDAC
    2008
    ACM
    103views Hardware» more  ASPDAC 2008»
    Dynamic supply noise measurement circuit composed of standard cells suitable for in-site SoC power integrity verification
    14 years 2 months ago
    Dynamic supply noise measurement circuit composed of standard cells suitable for in-site SoC power integrity verification
    Download  www.cecs.uci.edu
    This paper presents an all digital measurement circuit called "gated oscillator" for capturing waveforms of dynamic power supply noise. The gated oscillator is constructe...
    Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoy...
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    ASPDAC
    2008
    ACM
    104views Hardware» more  ASPDAC 2008»
    Pessimism reduction in coupling-aware static timing analysis using timing and logic filtering
    14 years 2 months ago
    Pessimism reduction in coupling-aware static timing analysis using timing and logic filtering
    Download  users.eecs.northwestern.edu
    With continued scaling of technology into nanometer regimes, the impact of coupling induced delay variations is significant. While several coupling-aware static timers have been pr...
    Debasish Das, Kip Killpack, Chandramouli V. Kashya...
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    ASPDAC
    2008
    ACM
    124views Hardware» more  ASPDAC 2008»
    MaizeRouter: Engineering an effective global router
    14 years 2 months ago
    MaizeRouter: Engineering an effective global router
    Download  www.eecs.umich.edu
    In this paper, we present the complete design and architectural details of MAIZEROUTER. MAIZEROUTER reflects a significant leap in progress over existing publicly available routing...
    Michael D. Moffitt
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    ASPDAC
    2008
    ACM
    77views Hardware» more  ASPDAC 2008»
    Symmetry-aware placement with transitive closure graphs for analog layout design
    14 years 2 months ago
    Symmetry-aware placement with transitive closure graphs for analog layout design
    Download  www.aspdac.com
    Lihong Zhang, C.-J. Richard Shi, Yingtao Jiang
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    ASPDAC
    2008
    ACM
    104views Hardware» more  ASPDAC 2008»
    Low power clock buffer planning methodology in F-D placement for large scale circuit design
    14 years 2 months ago
    Low power clock buffer planning methodology in F-D placement for large scale circuit design
    Download  dropzone.tamu.edu
    Traditionally, clock network layout is performed after cell placement. Such methodology is facing a serious problem in nanometer IC designs where people tend to use huge clock buff...
    Yanfeng Wang, Qiang Zhou, Yici Cai, Jiang Hu, Xian...
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    ASPDAC
    2008
    ACM
    85views Hardware» more  ASPDAC 2008»
    ORB: An on-chip optical ring bus communication architecture for multi-processor systems-on-chip
    14 years 2 months ago
    ORB: An on-chip optical ring bus communication architecture for multi-processor systems-on-chip
    Download  www.engr.colostate.edu
    Abstract
    Sudeep Pasricha, Nikil Dutt
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    ASPDAC
    2008
    ACM
    174views Hardware» more  ASPDAC 2008»
    Chebyshev Affine Arithmetic based parametric yield prediction under limited descriptions of uncertainty
    14 years 2 months ago
    Chebyshev Affine Arithmetic based parametric yield prediction under limited descriptions of uncertainty
    Download  www.cecs.uci.edu
    In modern circuit design, it is difficult to provide reliable parametric yield prediction since the real distribution of process data is hard to measure. Most existing approaches ...
    Jin Sun, Yue Huang, Jun Li, Janet Meiling Wang
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    ASPDAC
    2008
    ACM
    97views Hardware» more  ASPDAC 2008»
    A Compiler-in-the-Loop framework to explore Horizontally Partitioned Cache architectures
    14 years 2 months ago
    A Compiler-in-the-Loop framework to explore Horizontally Partitioned Cache architectures
    Download  www.ics.uci.edu
    Horizontally Partitioned Caches (HPCs) are a promising architectural feature to reduce the energy consumption of the memory subsystem. However, the energy reduction obtained using...
    Aviral Shrivastava, Ilya Issenin, Nikil Dutt
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