block-based statistical timing

32

ASPDAC
2010
ACM

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Statistical timing verification for transparently latched circuits through structural graph traversal

13 years 9 months ago

Level-sensitive transparent latches are widely used in high-performance sequential circuit designs. Under process variations, the timing of a transparently latched circuit will ada...

Xingliang Yuan, Jia Wang

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27

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TVLSI
2008

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Fast Estimation of Timing Yield Bounds for Process Variations

13 years 11 months ago

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With aggressive scaling down of feature sizes in VLSI fabrication, process variation has become a critical issue in designs. We show that two necessary conditions for the "Max...

Ruiming Chen, Hai Zhou

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26

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DAC
2004
ACM

94views Computer Architecture» more DAC 2004»

First-order incremental block-based statistical timing analysis

15 years 15 days ago

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Chandramouli Visweswariah, K. Ravindran, K. Kalafa...

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