Sciweavers

DATE
2004
IEEE
147views Hardware» more  DATE 2004»
14 years 3 months ago
Automatic Tuning of Two-Level Caches to Embedded Applications
The power consumed by the memory hierarchy of a microprocessor can contribute to as much as 50% of the total microprocessor system power, and is thus a good candidate for optimiza...
Ann Gordon-Ross, Frank Vahid, Nikil Dutt
GLVLSI
2005
IEEE
124views VLSI» more  GLVLSI 2005»
14 years 5 months ago
A first look at the interplay of code reordering and configurable caches
The instruction cache is a popular target for optimizations of microprocessor-based systems because of the cache’s high impact on system performance and power, and because of th...
Ann Gordon-Ross, Frank Vahid, Nikil Dutt
DATE
2007
IEEE
98views Hardware» more  DATE 2007»
14 years 5 months ago
A one-shot configurable-cache tuner for improved energy and performance
We introduce a new non-intrusive on-chip cache-tuning hardware module capable of accurately predicting the best configuration of a configurable cache for an executing application....
Ann Gordon-Ross, Pablo Viana, Frank Vahid, Walid A...