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ISCA
1998
IEEE
136views Hardware» more  ISCA 1998»
14 years 4 months ago
Exploiting Spatial Locality in Data Caches Using Spatial Footprints
Modern cache designs exploit spatial locality by fetching large blocks of data called cache lines on a cache miss. Subsequent references to words within the same cache line result...
Sanjeev Kumar, Christopher B. Wilkerson
ISCA
1998
IEEE
143views Hardware» more  ISCA 1998»
14 years 4 months ago
Lockup-Free Instruction Fetch/Prefetch Cache Organization
In the past decade. there has been much literature describing various cache organizatrons that exploit general programming idiosyncrasies to obtain maxrmum hit rate (the probabili...
David Kroft
ISHPC
1999
Springer
14 years 4 months ago
Utilization of Cache Area in On-Chip Multiprocessor
On-chip multiprocessor can be an alternative to the wide-issue superscalar processor approach which is currently the mainstream to exploit the increasing number of transistors on ...
Hitoshi Oi, N. Ranganathan
ICS
1999
Tsinghua U.
14 years 4 months ago
Reducing cache misses using hardware and software page placement
As the gap between memory and processor speeds continues to widen, cache efficiency is an increasingly important component of processor performance. Compiler techniques have been...
Timothy Sherwood, Brad Calder, Joel S. Emer
HIPC
1999
Springer
14 years 4 months ago
Microcaches
We describe a radically new cache architecture and demonstrate that it offers a huge reduction in cache cost, size and power consumption whilst maintaining performance on a wide ra...
David May, Dan Page, James Irwin, Henk L. Muller
WETICE
1999
IEEE
14 years 4 months ago
A Workgroup Model for Smart Pushing and Pulling
Our Workgroup Cache system operates as a virtual intranet, introducing a shared cache to members of the same workgroup. Users may be members of multiple workgroups at the same tim...
Gail E. Kaiser, Christopher Vaill, Stephen E. Doss...
EUROPAR
1999
Springer
14 years 4 months ago
Annotated Memory References: A Mechanism for Informed Cache Management
Processor cycle time continues to decrease faster than main memory access times, placing higher demands on cache memory hierarchy performance. To meet these demands, conventional ...
Alvin R. Lebeck, David R. Raymond, Chia-Lin Yang, ...
MTDT
1999
IEEE
68views Hardware» more  MTDT 1999»
14 years 4 months ago
Unbalanced Cache Systems
The new concept of an unbalanced, hierarchicallydivided cache memory system is introduced and analyzed. This approach generalizes existing cache structures by allowing different m...
David L. Rhodes, Wayne Wolf
MICRO
1999
IEEE
71views Hardware» more  MICRO 1999»
14 years 4 months ago
Selective Cache Ways: On-Demand Cache Resource Allocation
Increasing levels of microprocessor power dissipation call for new approaches at the architectural level that save energy by better matching of on-chip resources to application re...
David H. Albonesi
ISCA
1999
IEEE
187views Hardware» more  ISCA 1999»
14 years 4 months ago
Area Efficient Architectures for Information Integrity in Cache Memories
Information integrity in cache memories is a fundamental requirement for dependable computing. Conventional architectures for enhancing cache reliability using check codes make it...
Seongwoo Kim, Arun K. Somani