DAC
1997
ACM
13 years 11 months ago
1997
ACM
We propose a methodology for applying gate-level logic transformations to optimize power in digital circuits. Statistically simulated[14] switching information, gate delays, signa...
DAC
1997
ACM
13 years 11 months ago
1997
ACM
Abstract. Many modern systems are designed as a set of interconnected reactive subsystems. The subsystem verification task is to verify an implementation of the subsystem against t...
DAC
1997
ACM
13 years 11 months ago
1997
ACM
We present our experiences with the formal verification of an automotive chip used to control the safety features in a car. We used a BDD based model checker in our work. We descr...
DAC
1997
ACM
13 years 11 months ago
1997
ACM
Extracting the inductance of complex interconnect topologies is a formidable task, and simulating the resulting dense partial inductance matrix is even more difficult. Furthermore...
DAC
1997
ACM
13 years 11 months ago
1997
ACM
This paper describes a fully automatic standard-cell layout synthesis system, CELLERITY. The system is flexible in supporting a wide variety of process technologies and a range of...
DAC
1997
ACM
13 years 11 months ago
1997
ACM
This paper presents for the first time low energy simultaneous memory and register allocation. A minimum cost network flow approach is used to efficiently solve for minimum energy...
APCSAC
2000
IEEE
13 years 11 months ago
2000
IEEE
Dataflow computation models enable simpler and more efficient management of the memory hierarchy - a key barrier to the performance of many parallel programs. This paper describes...
DAC
2010
ACM
13 years 11 months ago
2010
ACM
The level of security provided by digital rights management functions and cryptographic protocols depend heavily on the security of an embedded secret key. The current practice of...
DAC
2010
ACM
13 years 11 months ago
2010
ACM
APCSAC
2003
IEEE
13 years 11 months ago
2003
IEEE
Very Long Instruction Word (VLIW) architectures exploit instruction level parallelism (ILP) with the help of the compiler to achieve higher instruction throughput with minimal hard...