Current Application Specific Instruction set Processor (ASIP) design methodologies are mostly based on iterative architecture exploration that uses Architecture Description Langua...
Kingshuk Karuri, Mohammad Abdullah Al Faruque, Ste...
This paper presents an efficient hierarchical 3D capacitance extraction algorithm -- ICCAP. Most previous capacitance extraction algorithms introduce intermediate variables to fac...
Leakage energy consumption is an increasing concern in current and future CMOS technologygenerations. Procrastination scheduling, where task execution can be delayed to maximize t...
el Predicate Abstraction and Refinement for Verifying RTL Verilog Himanshu Jain CMU SCS, Pittsburgh, PA 15213 Daniel Kroening ETH Z?urich, Switzerland Natasha Sharygina CMU SCS an...
Himanshu Jain, Daniel Kroening, Natasha Sharygina,...
- This paper proposes an approach for pixel transformation of the displayed image to increase the potential energy saving of the backlight scaling method. The proposed approach tak...
The race conditions often limit the smallest feasible clock period that the optimal clock skew scheduling can achieve. Therefore, the combination of clock skew scheduling and dela...
An efficient approach to full-wave impedance extraction is developed that accounts for substrate effects through the use of two-layer media Green's functions in a mixed-poten...
As technology advances into the nanometer territory, the interconnect delay has become a first-order effect on chip performance. To handle this effect, the X-architecture has been...
We describe IODINE, a tool to automatically extract likely design properties using dynamic analysis. A practical bottleneck in the formal verification of hardware designs is the n...
While the past research discussed several advantages of multiprocessor-system-on-a-chip (MPSOC) architectures from both area utilization and design verification perspectives over ...