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    DAC
    2005
    ACM
    118views Computer Architecture» more  DAC 2005»
    Power optimal dual-Vdd buffered tree considering buffer stations and blockages
    15 years 12 days ago
    Power optimal dual-Vdd buffered tree considering buffer stations and blockages
    Download  eda.ee.ucla.edu
    This paper presents the first in-depth study on applying dual Vdd buffers to buffer insertion and multi-sink buffered tree construction for power minimization under delay constrai...
    King Ho Tam, Lei He
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    DAC
    2005
    ACM
    89views Computer Architecture» more  DAC 2005»
    Path based buffer insertion
    15 years 12 days ago
    Path based buffer insertion
    Download  dropzone.tamu.edu
    Cliff C. N. Sze, Charles J. Alpert, Jiang Hu, Weip...
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    DAC
    2005
    ACM
    134views Computer Architecture» more  DAC 2005»
    Cache coherence support for non-shared bus architecture on heterogeneous MPSoCs
    15 years 12 days ago
    Cache coherence support for non-shared bus architecture on heterogeneous MPSoCs
    Download  users.ece.gatech.edu
    We propose two novel integration techniques -- bypass and bookkeeping -- in the memory controller to address the cache coherence compatibility issue of a non-shared bus heterogene...
    Taeweon Suh, Daehyun Kim, Hsien-Hsin S. Lee
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    DAC
    2005
    ACM
    123views Computer Architecture» more  DAC 2005»
    A quasi-convex optimization approach to parameterized model order reduction
    15 years 12 days ago
    A quasi-convex optimization approach to parameterized model order reduction
    Download  www.mit.edu
    In this paper an optimization based model order reduction (MOR) framework is proposed. The method involves setting up a quasiconvex program that explicitly minimizes a relaxation ...
    Kin Cheong Sou, Alexandre Megretski, Luca Daniel
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    DAC
    2005
    ACM
    134views Computer Architecture» more  DAC 2005»
    Robust gate sizing by geometric programming
    15 years 12 days ago
    Robust gate sizing by geometric programming
    Download  www.ece.umn.edu
    We present an efficient optimization scheme for gate sizing in the presence of process variations. Using a posynomial delay model, the delay constraints are modified to incorporat...
    Jaskirat Singh, Vidyasagar Nookala, Zhi-Quan Luo, ...
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    DAC
    2005
    ACM
    123views Computer Architecture» more  DAC 2005»
    Incremental retiming for FPGA physical synthesis
    15 years 12 days ago
    Incremental retiming for FPGA physical synthesis
    Download  www.eecg.toronto.edu
    In this paper, we present a new linear-time retiming algorithm that produces near-optimal results. Our implementation is specifically targeted at Altera's Stratix [1] FPGAbas...
    Deshanand P. Singh, Valavan Manohararajah, Stephen...
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    DAC
    2005
    ACM
    240views Computer Architecture» more  DAC 2005»
    FLEXBUS: a high-performance system-on-chip communication architecture with a dynamically configurable topology
    15 years 12 days ago
    FLEXBUS: a high-performance system-on-chip communication architecture with a dynamically configurable topology
    Download  esdat.ucsd.edu
    In this paper, we describe FLEXBUS, a flexible, high-performance onchip communication architecture featuring a dynamically configurable topology. FLEXBUS is designed to detect run...
    Krishna Sekar, Kanishka Lahiri, Anand Raghunathan,...
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    DAC
    2005
    ACM
    110views Computer Architecture» more  DAC 2005»
    Multi-threaded reachability
    15 years 12 days ago
    Multi-threaded reachability
    Download  chicory.stanford.edu
    Partitioned BDD-based algorithms have been proposed in the literature to solve the memory explosion problem in BDD-based verification. Such algorithms can be at times ineffective ...
    Debashis Sahoo, Jawahar Jain, Subramanian K. Iyer,...
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    DAC
    2005
    ACM
    159views Computer Architecture» more  DAC 2005»
    Towards scalable flow and context sensitive pointer analysis
    15 years 12 days ago
    Towards scalable flow and context sensitive pointer analysis
    Download  www.eecg.toronto.edu
    Pointer analysis, a classic problem in software program analysis, has emerged as an important problem to solve in design automation, at a time when complex designs, specified in t...
    Jianwen Zhu
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    DAC
    2005
    ACM
    126views Computer Architecture» more  DAC 2005»
    Energy optimal speed control of devices with discrete speed sets
    15 years 12 days ago
    Energy optimal speed control of devices with discrete speed sets
    Download  www.cs.york.ac.uk
    We obtain analytically, the energy optimal speed profile of a generic multi-speed device with a discrete set of speeds, to execute a given task within a given time. Current implem...
    Ravishankar Rao, Sarma B. K. Vrudhula
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