Sciweavers

DATE
2005
IEEE
117views Hardware» more  DATE 2005»
14 years 5 months ago
Extended Control Flow Graph Based Performance Optimization Using Scratch-Pad Memory
This paper presents an exploration approach for the researcher to choose the suitable size of Scratch-Pad memory (SPM) for maximal performance improvement of a specified applicat...
Pu Hanlai, Ling Ming, Jin Jing
DATE
2005
IEEE
112views Hardware» more  DATE 2005»
14 years 5 months ago
TDMA Time Slot and Turn Optimization with Evolutionary Search Techniques
In this paper we present arithmetic real-coded variation operators tailored for time slot and turn optimization on TDMA-scheduled resources with evolutionary algorithms. Our opera...
Arne Hamann, Rolf Ernst
DATE
2005
IEEE
131views Hardware» more  DATE 2005»
14 years 5 months ago
Unified Modeling of Complex Real-Time Control Systems
Complex real-time control system is a software dense and algorithms dense system, which needs modern software engineering techniques to design. UML is an object-oriented industria...
He Hai, Zhong Yi-fang, Cai Chi-lan
DATE
2005
IEEE
169views Hardware» more  DATE 2005»
14 years 5 months ago
Optimized Generation of Data-Path from C Codes for FPGAs
Zhi Guo, Betul Buyukkurt, Walid A. Najjar, Kees A....
DATE
2005
IEEE
119views Hardware» more  DATE 2005»
14 years 5 months ago
On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips
Multi-site testing is a popular and effective way to increase test throughput and reduce test costs. We present a test throughput model, in which we focus on wafer testing, and co...
Sandeep Kumar Goel, Erik Jan Marinissen
DATE
2005
IEEE
126views Hardware» more  DATE 2005»
14 years 5 months ago
An Efficient BICS Design for SEUs Detection and Correction in Semiconductor Memories
Balkaran S. Gill, Michael Nicolaidis, Francis G. W...
DATE
2005
IEEE
133views Hardware» more  DATE 2005»
14 years 5 months ago
Analog and Digital Circuit Design in 65 nm CMOS: End of the Road?
Georges G. E. Gielen, Wim Dehaene, Phillip Christi...
DATE
2005
IEEE
115views Hardware» more  DATE 2005»
14 years 5 months ago
Stochastic Power Grid Analysis Considering Process Variations
In this paper, we investigate the impact of interconnect and device process variations on voltage fluctuations in power grids. We consider random variations in the power grid’s...
Praveen Ghanta, Sarma B. K. Vrudhula, Rajendran Pa...
DATE
2005
IEEE
116views Hardware» more  DATE 2005»
14 years 5 months ago
A Complete Network-On-Chip Emulation Framework
Current Systems-On-Chip (SoC) execute applications that demand extensive parallel processing. Networks-OnChip (NoC) provide a structured way of realizing interconnections on silic...
Nicolas Genko, David Atienza, Giovanni De Micheli,...