DATE
2005
IEEE
14 years 5 months ago
2005
IEEE
DATE
2005
IEEE
14 years 5 months ago
2005
IEEE
Coarse-grained reconfigurable architectures aim to achieve both goals of high performance and flexibility. However, existing reconfigurable array architectures require many resour...
DATE
2005
IEEE
14 years 5 months ago
2005
IEEE
The new standard for digital video broadcast DVB-S2 features Low-Density Parity-Check (LDPC) codes as their channel coding scheme. The codes are defined for various code rates wi...
DATE
2005
IEEE
14 years 5 months ago
2005
IEEE
DATE
2005
IEEE
14 years 5 months ago
2005
IEEE
In this work we consider battery powered portable systems which either have Field Programmable Gate Arrays (FPGA) or voltage and frequency scalable processors as their main proces...
DATE
2005
IEEE
14 years 5 months ago
2005
IEEE
This paper describes two research projects that develop new low-cost techniques for testing devices with multiple high-speed (2 to 5 Gbps) signals. Each project uses commercially ...
DATE
2005
IEEE
14 years 5 months ago
2005
IEEE
In this paper, the program control unit of an embedded RISC processor is enhanced with a novel zerooverhead loop controller (ZOLC) supporting arbitrary loop structures with multip...
DATE
2005
IEEE
14 years 5 months ago
2005
IEEE
On-chip buses are typically designed to meet performance constraints at worst-case conditions, including process corner, temperature, IR-drop, and neighboring net switching patter...
DATE
2005
IEEE
14 years 5 months ago
2005
IEEE
DATE
2005
IEEE
14 years 5 months ago
2005
IEEE
Triple Modular Redundancy (TMR) is a suitable fault tolerant technique for SRAM-based FPGA. However, one of the main challenges in achieving 100% robustness in designs protected b...