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DATE
2005
IEEE
187views Hardware» more  DATE 2005»
14 years 5 months ago
Cycle Accurate Binary Translation for Simulation Acceleration in Rapid Prototyping of SoCs
In this paper, the application of a cycle accurate binary translator for rapid prototyping of SoCs will be presented. This translator generates code to run on a rapid prototyping ...
Jürgen Schnerr, Oliver Bringmann, Wolfgang Ro...
DATE
2005
IEEE
162views Hardware» more  DATE 2005»
14 years 5 months ago
A Model-Based Approach for Executable Specifications on Reconfigurable Hardware
UML 2.0 provides a rich set of diagrams for systems documentation and specification. Many efforts have been undertaken to employ different aspects of UML for multiple domains, mai...
Tim Schattkowsky, Wolfgang Müller 0003, Achim...
DATE
2005
IEEE
100views Hardware» more  DATE 2005»
14 years 5 months ago
UML 2.0 - Overview and Perspectives in SoC Design
The design productivity gap requires more efficient design methods. Software systems have faced the same challenge and seem to have mastered it with the
Tim Schattkowsky
DATE
2005
IEEE
121views Hardware» more  DATE 2005»
14 years 5 months ago
Fault-Trajectory Approach for Fault Diagnosis on Analog Circuits
This issue discusses the fault-trajectory approach suitability for fault diagnosis on analog networks. Recent works have shown promising results concerning a method based on this ...
Carlos Eduardo Savioli, Claudio C. Czendrodi, Jos&...
DATE
2005
IEEE
122views Hardware» more  DATE 2005»
14 years 5 months ago
Diagnostic and Detection Fault Collapsing for Multiple Output Circuits
We discuss fault equivalence and dominance relations for multiple output combinational circuits. The conventional definition for equivalence says that “Two faults are equivalen...
Raja K. K. R. Sandireddy, Vishwani D. Agrawal
DATE
2005
IEEE
117views Hardware» more  DATE 2005»
14 years 5 months ago
A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs
As technology scales down, the static power is expected to become a significant fraction of the total power. The exponential dependence of static power with the operating temperat...
José Luis Rosselló, Vicens Canals, S...
DATE
2005
IEEE
110views Hardware» more  DATE 2005»
14 years 5 months ago
Rapid Generation of Thermal-Safe Test Schedules
Overheating has been acknowledged as a major issue in testing complex SOCs. Several power constrained system-level DFT solutions (power constrained test scheduling) have recently ...
Paul M. Rosinger, Bashir M. Al-Hashimi, Krishnendu...
DATE
2005
IEEE
115views Hardware» more  DATE 2005»
14 years 5 months ago
An Infrastructure to Functionally Test Designs Generated by Compilers Targeting FPGAs
This paper presents an infrastructure to test the functionality of the specific architectures output by a highlevel compiler targeting dynamically reconfigurable hardware. It resu...
Rui Rodrigues, João M. P. Cardoso