DATE
2005
IEEE
14 years 5 months ago
2005
IEEE
Conventional cache models are not suited for real-time parallel processing because tasks may flush each other’s data out of the cache in an unpredictable manner. In this way th...
DATE
2005
IEEE
14 years 5 months ago
2005
IEEE
Functional verification of microprocessors is one of the most complex and expensive tasks in the current system-on-chip design process. A significant bottleneck in the validatio...
DATE
2005
IEEE
14 years 5 months ago
2005
IEEE
A class of discrete event synthesis problems can be reduced to solving language equations F • X ⊆ S, where F is the fixed component and S the specification. Sequential synthes...
DATE
2005
IEEE
14 years 5 months ago
2005
IEEE
This paper describes an improved approach to Boolean network optimization using internal don’t-cares. The improvements concern the type of don’t-cares computed, their scope, a...
DATE
2005
IEEE
14 years 5 months ago
2005
IEEE
DATE
2005
IEEE
14 years 5 months ago
2005
IEEE
—Presented are a methodology and a DFII-based tool for AC-stability analysis of a wide variety of closed-loop continuous-time (operational amplifiers and other linear circuits). ...
DATE
2005
IEEE
14 years 5 months ago
2005
IEEE
Transient errors are one of the major reasons for system downtime in many systems. While prior research has mainly focused on the impact of transient errors on datapath, caches an...
DATE
2005
IEEE
14 years 5 months ago
2005
IEEE
Let’s be clear from the outset: SoC can most certainly make use of UML; SoC just doesn’t need more UML, or even all of it. The advent of model mappings, coupled with marks tha...
DATE
2005
IEEE
14 years 5 months ago
2005
IEEE
DATE
2005
IEEE
14 years 5 months ago
2005
IEEE