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DATE
2009
IEEE
180views Hardware» more  DATE 2009»
14 years 6 months ago
FSAF: File system aware flash translation layer for NAND Flash Memories
NAND Flash Memories require Garbage Collection (GC) and Wear Leveling (WL) operations to be carried out by Flash Translation Layers (FTLs) that oversee flash management. Owing to ...
Sai Krishna Mylavarapu, Siddharth Choudhuri, Avira...
DATE
2009
IEEE
88views Hardware» more  DATE 2009»
14 years 6 months ago
Program phase and runtime distribution-aware online DVFS for combined Vdd/Vbb scaling
Abstract—Complex software programs are mostly characterized by phase behavior and runtime distributions. Due to the dynamism of the two characteristics, it is not efficient to m...
Jungsoo Kim, Sungjoo Yoo, Chong-Min Kyung
DATE
2009
IEEE
102views Hardware» more  DATE 2009»
14 years 6 months ago
Register placement for high-performance circuits
—In modern sub-micron design, achieving low-skew clock distributions is facing challenges for high-performance circuits. Symmetric global clock distribution and clock tree synthe...
Mei-Fang Chiang, Takumi Okamoto, Takeshi Yoshimura
DATE
2009
IEEE
122views Hardware» more  DATE 2009»
14 years 6 months ago
Co-simulation based platform for wireless protocols design explorations
Abstract—Longer range, faster speed and stronger link are today’s wireless mandatory characteristics. Tremendous efforts are being deployed to create new and improved wireless ...
Alain Fourmigue, Bruno Girodias, Gabriela Nicolesc...
DATE
2009
IEEE
92views Hardware» more  DATE 2009»
14 years 6 months ago
Strengthening properties using abstraction refinement
Mitra Purandare, Thomas Wahl, Daniel Kroening
DATE
2009
IEEE
127views Hardware» more  DATE 2009»
14 years 6 months ago
Sequential logic synthesis using symbolic bi-decomposition
This paper uses under-approximation of unreachable states of a design to derive incomplete specification of combinational logic. The resulting incompletely-specified functions are...
Victor N. Kravets, Alan Mishchenko
DATE
2009
IEEE
110views Hardware» more  DATE 2009»
14 years 6 months ago
Analog layout synthesis - Recent advances in topological approaches
Helmut Gräb, Florin Balasa, R. Castro-L&oacut...
DATE
2009
IEEE
98views Hardware» more  DATE 2009»
14 years 6 months ago
Test architecture design and optimization for three-dimensional SoCs
Core-based system-on-chips (SoCs) fabricated on threedimensional (3D) technology are emerging for better integration capabilities. Effective test architecture design and optimizat...
Li Jiang, Lin Huang, Qiang Xu
DATE
2009
IEEE
151views Hardware» more  DATE 2009»
14 years 6 months ago
pTest: An adaptive testing tool for concurrent software on embedded multicore processors
—More and more processor manufacturers have launched embedded multicore processors for consumer electronics products because such processors provide high performance and low powe...
Shou-Wei Chang, Kun-Yuan Hsieh, Jenq Kuen Lee
DATE
2009
IEEE
105views Hardware» more  DATE 2009»
14 years 6 months ago
Exploiting narrow-width values for thermal-aware register file designs
—Localized heating-up creates thermal hotspots across the chip, with the integer register file ranked as the hottest unit in high-performance microprocessors. In this paper, we ...
Shuai Wang, Jie Hu, Sotirios G. Ziavras, Sung Woo ...