—This paper presents a tool for exploring different parallelization options for an application. It can be used to quickly find a high-quality match between an application and a ...
Rogier Baert, Erik Brockmeyer, Sven Wuytack, Thoma...
—This paper presents a new two-levels page-based memory bus protection scheme. A trusted Operating System drives a hardware cryptographic unit and manages security contexts for e...
Lifeng Su, Stephan Courcambeck, Pierre Guillemin, ...
— Fault injection has become a very classical method to determine the dependability of an integrated system with respect to soft errors. Due to the huge number of possible error ...
—Redundancy Addition and Removal (RAR) is a restructuring technique used in the synthesis and optimization of logic designs. It can remove an existing target wire and add an alte...
In this work, the focus is put on the behavior of a system in case a fault occurs that disables the system from executing its applications. Instead of executing a random subset of...
Abstract—This paper summarizes a special session on multicore/multi-processor system-on-chip (MPSoC) programming challenges. The current trend towards MPSoC platforms in most com...
Rainer Leupers, Andras Vajda, Marco Bekooij, Soonh...
— Memories are increasingly dominating Systems on Chip (SoC) designs and thus contribute a large percentage of the total system’s power dissipation, area and reliability. In th...
Amin Khajeh, Aseem Gupta, Nikil Dutt, Fadi J. Kurd...
—In this paper, we propose a scalable and transparent parallelization scheme using threads for multi-core processor. The performance achieved by our scheme is scalable to the num...
In this work, we propose an enhanced design method for filterless class-D audio amplifier based on multilevel architecture. The multilevel technique consists of a multilevel conve...