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ET
2010
98views more  ET 2010»
13 years 9 months ago
MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics
Abstract As technology scales down into the nanometer era, delay testing of modern chips has become more and more important. Tests for the path delay fault model are widely used to...
Stephan Eggersglüß, Görschwin Fey,...
ICCAD
1994
IEEE
87views Hardware» more  ICCAD 1994»
14 years 3 months ago
On testing delay faults in macro-based combinational circuits
We consider the problem of testing for delay faults in macrobased circuits. Macro-based circuits are obtained as a result of technology mapping. Gate-level fault models cannot be ...
Irith Pomeranz, Sudhakar M. Reddy
GLVLSI
2002
IEEE
136views VLSI» more  GLVLSI 2002»
14 years 4 months ago
Test generation for resistive opens in CMOS
This paper develops new techniques for detecting both stuck-open faults and resistive open faults, which result in increased delays along some paths. The improved detection of CMO...
Arun Krishnamachary, Jacob A. Abraham
ICCD
2007
IEEE
125views Hardware» more  ICCD 2007»
14 years 8 months ago
Low-cost run-time diagnosis of hard delay faults in the functional units of a microprocessor
This paper addresses the run-time diagnosis of delay faults in functional units of microprocessors. Despite the popularity of the stuck-at fault model, it is no longer the only re...
Sule Ozev, Daniel J. Sorin, Mahmut Yilmaz