Since across-chip interconnect delays can exceed a clock cycle in nanometer technologies, it has become essential in high performance designs to add flip-flops on wires with multi...
Vidyasagar Nookala, Ying Chen, David J. Lilja, Sac...
As the process technology enters the nanometer era, reliability has become a major concern in the design and manufacturing of VLSI circuits. In this paper we focus on one reliabil...
Physical phenomena such as temperature have an increasingly important role in performance and reliability of modern process technologies. This trend will only strengthen with futu...
Rajarshi Mukherjee, Seda Ogrenci Memik, Gokhan Mem...
We present several improvements to general-purpose sequential redundancy removal. First, we propose using a robust variety of synergistic transformation and verification algorithm...
Hari Mony, Jason Baumgartner, Viresh Paruthi, Robe...
Channel estimation and multiuser detection are enabling technologies for future generations of wireless applications. However, sophisticated algorithms are required for accurate c...
Yan Meng, Andrew P. Brown, Ronald A. Iltis, Timoth...
This paper presents a unifying framework for the modeling of asynchronous pipeline circuits. A pipeline protocol is captured in a graph-based model which defines the partial order...
As feature sizes shrink, transient failures of on-chip network links become a critical problem. At the same time, many applications require guarantees on both message arrival prob...
Power minimization under variability is formulated as a rigorous statistical robust optimization program with a guarantee of power and timing yields. Both power and timing metrics...