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    DAC
    2005
    ACM
    125views Computer Architecture» more  DAC 2005»
    Architecture-adaptive range limit windowing for simulated annealing FPGA placement
    15 years 15 days ago
    Architecture-adaptive range limit windowing for simulated annealing FPGA placement
    Download  www.ee.washington.edu
    Previous research has shown both theoretically and practically that simulated annealing can greatly benefit from the incorporation of an adaptive range limiting window to control ...
    Kenneth Eguro, Scott Hauck, Akshay Sharma
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    DAC
    2005
    ACM
    88views Computer Architecture» more  DAC 2005»
    From myth to methodology: cross-layer design for energy-efficient wireless communication
    15 years 15 days ago
    From myth to methodology: cross-layer design for energy-efficient wireless communication
    Download  www.dcc.unicamp.br
    Wolfgang Eberle, Bruno Bougard, Sofie Pollin, Fran...
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    DAC
    2005
    ACM
    115views Computer Architecture» more  DAC 2005»
    Automated nonlinear Macromodelling of output buffers for high-speed digital applications
    15 years 15 days ago
    Automated nonlinear Macromodelling of output buffers for high-speed digital applications
    Download  potol.eecs.berkeley.edu
    We present applications of a recently developed automated nonlinear macromodelling approach to the important problem of macromodelling high-speed output buffers/drivers. Good nonl...
    Ning Dong, Jaijeet S. Roychowdhury
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    DAC
    2005
    ACM
    176views Computer Architecture» more  DAC 2005»
    Power emulation: a new paradigm for power estimation
    15 years 15 days ago
    Power emulation: a new paradigm for power estimation
    Download  mesl.ucsd.edu
    In this work, we propose a new paradigm called power emulation, which exploits hardware acceleration to drastically speedup power estimation. Power emulation is based on the obser...
    Joel Coburn, Srivaths Ravi, Anand Raghunathan
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    DAC
    2005
    ACM
    161views Computer Architecture» more  DAC 2005»
    Power-aware placement
    15 years 15 days ago
    Power-aware placement
    Download  ic.engin.brown.edu
    Lowering power is one of the greatest challenges facing the IC industry today. We present a power-aware placement method that simultaneously performs (1) activity-based register c...
    Yongseok Cheon, Pei-Hsin Ho, Andrew B. Kahng, Sher...
    posted by sreda
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    DAC
    2005
    ACM
    109views Computer Architecture» more  DAC 2005»
    Device and architecture co-optimization for FPGA power reduction
    15 years 15 days ago
    Device and architecture co-optimization for FPGA power reduction
    Download  www.ee.ucla.edu
    Device optimization considering supply voltage Vdd and threshold voltage Vt tuning does not increase chip area but has a great impact on power and performance in the nanometer tec...
    Lerong Cheng, Phoebe Wong, Fei Li, Yan Lin, Lei He
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    DAC
    2005
    ACM
    130views Computer Architecture» more  DAC 2005»
    Improving java virtual machine reliability for memory-constrained embedded systems
    15 years 15 days ago
    Improving java virtual machine reliability for memory-constrained embedded systems
    Download  www.cse.psu.edu
    Dual-execution/checkpointing based transient error tolerance techniques have been widely used in the high-end mission critical systems. These techniques, however, are not very att...
    Guangyu Chen, Mahmut T. Kandemir
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    DAC
    2005
    ACM
    149views Computer Architecture» more  DAC 2005»
    Simulation based deadlock analysis for system level designs
    15 years 15 days ago
    Simulation based deadlock analysis for system level designs
    Download  www.cs.ucr.edu
    In the design of highly complex, heterogeneous, and concurrent systems, deadlock detection and resolution remains an important issue. In this paper, we systematically analyze the ...
    Xi Chen, Abhijit Davare, Harry Hsieh, Alberto L. S...
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    DAC
    2005
    ACM
    145views Computer Architecture» more  DAC 2005»
    Full-chip analysis of leakage power under process variations, including spatial correlations
    15 years 15 days ago
    Full-chip analysis of leakage power under process variations, including spatial correlations
    Download  www.ece.umn.edu
    In this paper, we present a method for analyzing the leakage current, and hence the leakage power, of a circuit under process parameter variations that can include spatial correla...
    Hongliang Chang, Sachin S. Sapatnekar
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    DAC
    2005
    ACM
    128views Computer Architecture» more  DAC 2005»
    A novel synthesis approach for active leakage power reduction using dynamic supply gating
    15 years 15 days ago
    A novel synthesis approach for active leakage power reduction using dynamic supply gating
    Download  www.inf.ethz.ch
    : Due to exponential increase in subthreshold leakage with technology scaling and temperature increase, leakage power is becoming a major fraction of total power in the active mode...
    Swarup Bhunia, Nilanjan Banerjee, Qikai Chen, Hami...
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