Sciweavers

DAC
2003
ACM
15 years 15 days ago
Accurate timing analysis by modeling caches, speculation and their interaction
Schedulability analysis of real-time embedded systems requires worst case timing guarantees of embedded software performance. This involves not only language level program analysi...
Xianfeng Li, Tulika Mitra, Abhik Roychoudhury
DAC
2003
ACM
15 years 15 days ago
Analog and RF circuit macromodels for system-level analysis
Design and validation of mixed-signal integrated systems require evel model abstractions. Generalized Volterra series based models have been successfully applied for analog and RF...
Xin Li, Peng Li, Yang Xu, Lawrence T. Pileggi
DAC
2003
ACM
15 years 15 days ago
Multilevel floorplanning/placement for large-scale modules using B*-trees
We present in this paper a multilevel floorplanning/placement framework based on the B*-tree representation, called MB*-tree, to handle the floorplanning and packing for large-sca...
Hsun-Cheng Lee, Yao-Wen Chang, Jer-Ming Hsu, Hanna...
DAC
2003
ACM
15 years 15 days ago
A complexity effective communication model for behavioral modeling of signal processing applications
In this paper, we argue that the address space of memory regions that participate in inter task communication is over-specified by the traditional communication models used in beh...
M. N. V. Satya Kiran, M. N. Jayram, Pradeep Rao, S...
DAC
2003
ACM
15 years 15 days ago
Data communication estimation and reduction for reconfigurable systems
Widespread adoption of reconfigurable devices requires system level synthesis techniques to take an application written in a high level language and map it to the reconfigurable d...
Adam Kaplan, Philip Brisk, Ryan Kastner
DAC
2003
ACM
15 years 15 days ago
SAT-based unbounded symbolic model checking
Hyeong-Ju Kang, In-Cheol Park
DAC
2003
ACM
15 years 15 days ago
Generalized cofactoring for logic function evaluation
Yunjian Jiang, Slobodan Matic, Robert K. Brayton
DAC
2003
ACM
15 years 15 days ago
Embedded intelligent SRAM
Many embedded systems use a simple pipelined RISC processor for computation and an on-chip SRAM for data storage. We present an enhancement called Intelligent SRAM (ISRAM) that co...
Prabhat Jain, G. Edward Suh, Srinivas Devadas