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ERSA
2006
111views Hardware» more  ERSA 2006»
14 years 1 months ago
Promises and Pitfalls of Reconfigurable Supercomputing
Reconfigurable supercomputing (RSC) combines programmable logic chips with high performance microprocessors, all communicating over a high bandwidth, low latency interconnection n...
Maya Gokhale, Christopher Rickett, Justin L. Tripp...
ERSA
2006
89views Hardware» more  ERSA 2006»
14 years 1 months ago
Multi-Mode Operator for SHA-2 Hash Functions
We propose an improved implementation of the SHA-2 hash family to include a multi-mode of operation with minimal latency and hardware requirements over the entire operator. The mul...
Ryan Glabb, Laurent Imbert, Graham A. Jullien, Arn...
ERSA
2006
124views Hardware» more  ERSA 2006»
14 years 1 months ago
RTOS-Based Hardware Software Communications and Configuration Management in the Context of a Smart Camera
This paper deals with the question of task communication and configuration dynamic management in the context of hardware and software implementations. Our approach is based on a c...
Yvan Eustache, Jean-Philippe Diguet, Milad El Khod...
ERSA
2006
282views Hardware» more  ERSA 2006»
14 years 1 months ago
SyCERS: a SystemC Design Exploration Framework for SoC Reconfigurable Architecture
Reconfigurable devices, such as FPGAs, introduce into the design workflow of embedded systems a new degree of freedom: the designer can have the system autonomously modify the fun...
Carlo Amicucci, Fabrizio Ferrandi, Marco D. Santam...
ERSA
2006
109views Hardware» more  ERSA 2006»
14 years 1 months ago
Synthesis of Object Oriented Models on Reconfigurable Hardware
Abstract-- In this work the problem of modeling reconfigurable systems behavior with a precise, executable semantics is considered. The possibility of synthesising such models onto...
Giovanni Agosta, Francesco Bruschi, Marco D. Santa...
ERSA
2006
186views Hardware» more  ERSA 2006»
14 years 1 months ago
The Case for High Level Programming Models for Reconfigurable Computers
In this paper we first outline and discuss the issues of currently accepted computational models for hybrid CPU/FPGA systems. Then, we discuss the need for researchers to develop ...
David L. Andrews, Ron Sass, Erik Anderson, Jason A...
ERSA
2006
91views Hardware» more  ERSA 2006»
14 years 1 months ago
Intrinsic Embedded Hardware Evolution of Block-based Neural Networks
- An intrinsic embedded online evolution system has been designed using Block-based neural networks and implemented on Xilinx VirtexIIPro FPGAs. The designed network can dynamicall...
Saumil Merchant, Gregory D. Peterson, Seong Kong
ERSA
2006
98views Hardware» more  ERSA 2006»
14 years 1 months ago
Hydra: An Energy-efficient and Reconfigurable Network Interface
Abstract-- In heterogeneous tiled System-on-Chip architectures a Network-on-Chip is used to transport messages between processing elements. A reconfigurable network interface is us...
Marcel D. van de Burgwal, Gerard J. M. Smit, Gerar...
ERSA
2006
105views Hardware» more  ERSA 2006»
14 years 1 months ago
A Column Arrangement Algorithm for a Coarse-grained Reconfigurable Architecture
In a coarse-grained reconfigurable architecture, the functions of resources such as Arithmetic Logic Units (ALUs) can be reconfigured. Unlike the programmability of a general purp...
Yuanqing Guo, Cornelis Hoede, Gerard J. M. Smit
ERSA
2006
70views Hardware» more  ERSA 2006»
14 years 1 months ago
Differential Reconfiguration Architecture suitable for a Holographic Memory
Optically Reconfigurable Gate Arrays (ORGAs), by exploiting the large storage capacity of holographic memory, offer the possibility of providing a virtual gate count that is much l...
Minoru Watanabe, Mototsugu Miyano, Fuminori Kobaya...