A considerable portion of a chip is dedicated to a cache memory in a modern microprocessor chip. However, some applications may not actively need all the cache storage, especially...
The fastest known algorithms for factoring large numbers share a core sieving technique. The sieving cores find numbers that are completely factored over a prime base set raised t...
With the expiration of the Data Encryption Standard (DES) in 1998, the Advanced Encryption Standard (AES) development process is well underway. It is hoped that the result of the ...
In this paper we present a "high-level" FPGA architecture description language which lets FPGA architects succinctly and quickly describe an FPGA routing architecture. W...
In this paper, we study the technology mapping problem for a novel FPGA architecture that is based on k-input single-output PLA-like cells, or, k/m-macrocells. Each cell in this a...
In this paper we revisit the FPGA architectural issue of the effect of logic block functionality on FPGA performance and density. In particular, in the context of lookup table, cl...