ISCA
2010
IEEE
13 years 11 months ago
2010
IEEE
Due to their high volume, general-purpose processors, and now chip multiprocessors (CMPs), are much more cost effective than ASICs, but lag significantly in terms of performance a...
TVLSI
2002
14 years 7 days ago
2002
This paper presents the development of instruction analysis/scheduling CAD techniques to measure the distribution of functional unit usage and the micro operation level parallelis...
ISCA
1992
IEEE
14 years 4 months ago
1992
IEEE
In this paper, we propose a multithreaded processor architecture which improves machine throughput. In our processor architecture, instructions from different threads (not a singl...
DATE
2003
IEEE
14 years 5 months ago
2003
IEEE
A hardware method for functional unit assignment is presented, based on the principle that a functional unit’s power consumption is approximated by the switching activity of its...
IPCCC
2007
IEEE
14 years 7 months ago
2007
IEEE
Leakage power is a major concern in current microarchitectures as it is increasing exponentially with decreasing transistor feature sizes. In this paper, we present a technique ca...
DATE
2007
IEEE
14 years 7 months ago
2007
IEEE
Conventional high-level synthesis algorithms usually employ multi-cycle operators to reduce the cycle length in order to improve the circuit performance. These operators need seve...