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DFT
2005
IEEE
132views VLSI» more  DFT 2005»
14 years 1 months ago
Low Power BIST Based on Scan Partitioning
A built-in self-test (BIST) scheme is presented which both reduces overhead for detecting random-pattern-resistant (r.p.r.) faults as well as reduces power consumption during test...
Jinkyu Lee, Nur A. Touba
ICPP
1996
IEEE
14 years 3 months ago
A Timestamp-based Selective Invalidation Scheme for Multiprocessor Cache Coherence
- Among all software cache coherence strategaes, the ones that are based on the concept of tamestamps show the greatest potentaal an terms of cache performance. The early tamestamp...
Xin Yuan, Rami G. Melhem, Rajiv Gupta
ASPDAC
1998
ACM
105views Hardware» more  ASPDAC 1998»
14 years 3 months ago
Techniques for Functional Test Pattern Execution
Functional debugging often dominates the time and cost of the ASIC system development, mainly due to the limited controllability and observability of the storage elements in desig...
Inki Hong, Miodrag Potkonjak
DATE
2010
IEEE
161views Hardware» more  DATE 2010»
14 years 4 months ago
BISD: Scan-based Built-In self-diagnosis
Abstract—Built-In Self-Test (BIST) is less often applied to random logic than to embedded memories due to the following reasons: Firstly, for a satisfiable fault coverage it may...
Melanie Elm, Hans-Joachim Wunderlich
VTS
2003
IEEE
127views Hardware» more  VTS 2003»
14 years 4 months ago
Bist Reseeding with very few Seeds
Reseeding is used to improve fault coverage of pseudorandom testing. The seed corresponds to the initial state of the LFSR before filling the scan chain. The number of determinist...
Ahmad A. Al-Yamani, Subhasish Mitra, Edward J. McC...