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DFT
2008
IEEE
117views VLSI» more  DFT 2008»
14 years 3 months ago
Impact of Technology and Voltage Scaling on the Soft Error Susceptibility in Nanoscale CMOS
With each technology node shrink, a silicon chip becomes more susceptible to soft errors. The susceptibility further increases as the voltage is scaled down to save energy. Based ...
Vikas Chandra, Robert C. Aitken
DFT
2008
IEEE
86views VLSI» more  DFT 2008»
14 years 3 months ago
On Reducing Circuit Malfunctions Caused by Soft Errors
Ilia Polian, Sudhakar M. Reddy, Irith Pomeranz, Xu...
DFT
2008
IEEE
107views VLSI» more  DFT 2008»
14 years 3 months ago
Checkpointing of Rectilinear Growth in DNA Self-Assembly
Error detection/correction techniques have been advocated for algorithmic self-assembly. Under rectilinear growth, it requires only two additional tiles, generally referred to as ...
Stephen Frechette, Yong-Bin Kim, Fabrizio Lombardi
DFT
2008
IEEE
103views VLSI» more  DFT 2008»
14 years 3 months ago
Arbitrary Error Detection in Combinational Circuits by Using Partitioning
The paper presents a new technique for designing a concurrently checking combinational circuit. The technique is based on partitioning the circuit into two independent sub-circuit...
Osnat Keren, Ilya Levin, Vladimir Ostrovsky, Beni ...
DFT
2008
IEEE
82views VLSI» more  DFT 2008»
14 years 3 months ago
Selective Hardening of NanoPLA Circuits
Nanoelectronic components are expected to suffer from very high error rates, implying the need for hardening techniques. We propose a fine-grained approach to harden a promising...
Ilia Polian, Wenjing Rao
DFT
2008
IEEE
86views VLSI» more  DFT 2008»
14 years 3 months ago
Enhancing Silicon Debug via Periodic Monitoring
Scan-based debug methods give high observability of internal signals, however, they require halting the system to scan out responses from the circuit-under-debug (CUD). This is ti...
Joon-Sung Yang, Nur A. Touba
DFT
2008
IEEE
106views VLSI» more  DFT 2008»
14 years 3 months ago
Built-In Proactive Tuning System for Circuit Aging Resilience
VLSI circuits in nanometer VLSI technology experience significant aging effects, which are embodied by performance degradation over operation time. Although this degradation can b...
Nimay Shah, Rupak Samanta, Ming Zhang, Jiang Hu, D...
DFT
2008
IEEE
120views VLSI» more  DFT 2008»
14 years 3 months ago
Built-in-Self-Diagnostics for a NoC-Based Reconfigurable IC for Dependable Beamforming Applications
Integrated circuits (IC) targeting at the streaming applications for tomorrow are becoming a fast growing market. Applications such as beamforming require mass computing capabilit...
Oscar Kuiken, Xiao Zhang, Hans G. Kerkhoff
DFT
2008
IEEE
138views VLSI» more  DFT 2008»
14 years 3 months ago
Exploring Density-Reliability Tradeoffs on Nanoscale Substrates: When do smaller less reliable devices make sense?
It is widely recognized that device and interconnect fabrics at the nanoscale will be characterized by an increased susceptibility to transient faults. This appears to be intrinsi...
Andrey V. Zykov, Gustavo de Veciana
DEPCOS
2008
IEEE
156views Hardware» more  DEPCOS 2008»
14 years 3 months ago
A True Random Number Generator with Built-in Attack Detection
True random number generators (TRNGs) are extensively used in cryptography, simulations and statistics. Metastability is a way to generate true random numbers. By using electromag...
Bernhard Fechner, Andre Osterloh