Sciweavers

DATE
2008
IEEE
119views Hardware» more  DATE 2008»
14 years 3 months ago
Guiding Circuit Level Fault-Tolerance Design with Statistical Methods
In the last decade, the focus of fault-tolerance methods has tended towards circuit level modifications, such as transistor resizing, and away from expensive system level redunda...
Drew C. Ness, David J. Lilja
DATE
2008
IEEE
139views Hardware» more  DATE 2008»
14 years 3 months ago
Scan Chain Organization for Embedded Diagnosis
Keeping diagnostic resolution as high as possible while maximizing the compaction ratio is subject to research since the advent of embedded test. In this paper, we present a novel...
Melanie Elm, Hans-Joachim Wunderlich
DATE
2008
IEEE
116views Hardware» more  DATE 2008»
14 years 3 months ago
Fast Analog Circuit Synthesis Using Sensitivity Based Near Neighbor Searches
We present an efficient analog synthesis algorithm employing regression models of circuit matrices. Circuit matrix models achieve accurate and speedy synthesis of analog circuits...
Almitra Pradhan, Ranga Vemuri
DATE
2008
IEEE
142views Hardware» more  DATE 2008»
14 years 3 months ago
Developing Mesochronous Synchronizers to Enable 3D NoCs
The NETWORK-ON-CHIP (NOC) interconnection paradigm has been gaining momentum thanks to its flexibility, scalability and suitability to deep submicron technology processes. The ne...
Igor Loi, Federico Angiolini, Luca Benini
DATE
2008
IEEE
71views Hardware» more  DATE 2008»
14 years 3 months ago
Efficient Symbolic Simulation of Low Level Software
Tamarah Arons, Elad Elster, Shlomit Ozer, Jonathan...
DATE
2008
IEEE
95views Hardware» more  DATE 2008»
14 years 3 months ago
Improvements in Polynomial-Time Feasibility Testing for EDF
This paper presents two fully polynomial-time sufficient feasibility tests for EDF when considering periodic tasks with arbitrary deadlines and preemptive scheduling on uniproces...
Alejandro Masrur, Sebastian Drossler, Georg Farber
DATE
2008
IEEE
143views Hardware» more  DATE 2008»
14 years 3 months ago
Improving Synthesis of Compressor Trees on FPGAs via Integer Linear Programming
Multi-input addition is an important operation for many DSP and video processing applications. On FPGAs, multi-input addition has traditionally been implemented using trees of car...
Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne
DATE
2008
IEEE
157views Hardware» more  DATE 2008»
14 years 3 months ago
Clock Distribution Scheme using Coplanar Transmission Lines
The current work describes a new standing wave oscillator scheme aimed for clock propagation on coplanar transmission lines on a silicon die. The design is aimed for clock signali...
Victor H. Cordero, Sunil P. Khatri
DATE
2008
IEEE
140views Hardware» more  DATE 2008»
14 years 3 months ago
FPGA Design for Algebraic Tori-Based Public-Key Cryptography
Algebraic torus-based cryptosystems are an alternative for Public-Key Cryptography (PKC). It maintains the security of a larger group while the actual computations are performed i...
Junfeng Fan, Lejla Batina, Kazuo Sakiyama, Ingrid ...