Sciweavers

DATE
2008
IEEE
116views Hardware» more  DATE 2008»
14 years 3 months ago
Zero-Efficient Buffer Design for Reliable Network-on-Chip in Tiled Chip-Multi-Processor
Jun Wang, Hongbo Zeng, Kun Huang, Ge Zhang, Yan Ta...
DATE
2008
IEEE
182views Hardware» more  DATE 2008»
14 years 3 months ago
An adaptable FPGA-based System for Regular Expression Matching
In many applications string pattern matching is one of the most intensive tasks in terms of computation time and memory accesses. Network Intrusion Detection Systems and DNA Seque...
Ivano Bonesana, Marco Paolieri, Marco D. Santambro...
DATE
2008
IEEE
82views Hardware» more  DATE 2008»
14 years 3 months ago
A Triple-Mode Reconfigurable Sigma-Delta Modulator for Multi-Standard Wireless Applications
This paper presents the implementation and experimental characterization of a reconfigurable ΣΔ modulator intended for multi-mode wireless receivers that is capable to perform t...
Alonso Morgado, Rocio del Río, José ...
DATE
2008
IEEE
137views Hardware» more  DATE 2008»
14 years 3 months ago
SPARE - a Scalable algorithm for passive, structure preserving, Parameter-Aware model order REduction
In this paper we describe a flexible and efficient new algorithm for model order reduction of parameterized systems. The method is based on the reformulation of the parametric s...
Jorge Fernandez Villena, Luis Miguel Silveira
DATE
2008
IEEE
107views Hardware» more  DATE 2008»
14 years 3 months ago
Instruction Set Extension Exploration in Multiple-Issue Architecture
To satisfy high-performance computing demand in modern embedded devices, current embedded processor architectures provide designer with possibility either to define customized ins...
I-Wei Wu, Zhi-Yuan Chen, Jean Jyh-Jiun Shann, Chun...
DATE
2008
IEEE
122views Hardware» more  DATE 2008»
14 years 3 months ago
Digital bit stream jitter testing using jitter expansion
This paper presents a time-domain jitter expansion technique for high-speed digital bit sequence jitter testing. While jitter expansion has been applied to phase noise measurement...
Hyun Choi, Abhijit Chatterjee
DATE
2008
IEEE
75views Hardware» more  DATE 2008»
14 years 3 months ago
Wire Sizing Alternative - An Uniform Dual-rail Routing Architecture
To achieve minimum signal propagation delay, the nonuniform wire width routing architecture has been widely used in modern VLSI design. The non-uniform routing architecture exploi...
Fu-Wei Chen, Yi-Yu Liu
DATE
2008
IEEE
99views Hardware» more  DATE 2008»
14 years 3 months ago
Subsystem Exchange in a Concurrent Design Process Environment
This paper provides insight into the novel solutions used to build SoCs targeting increased productivity in a complex environment. Design of such SoCs relies on multi-team, multi-...
Marino Strik, Alain Gonier, Paul Williams
DATE
2008
IEEE
99views Hardware» more  DATE 2008»
14 years 3 months ago
GMDS: Hardware implementation of novel real output queuing architecture
In this paper, a real output queuing switch prototype implementation is presented. This implementation is based on a novel high speed multidrop backplane and a general purpose lin...
R. Arteaga, Félix Tobajas, Roberto Esper-Ch...