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MICRO
2000
IEEE
95views Hardware» more  MICRO 2000»
13 years 7 months ago
Predicting the Future
We present a novel methodology for predicting future outcomes that uses small numbers of individuals participating in an imperfect information market. By determining their risk att...
MICRO
2000
IEEE
95views Hardware» more  MICRO 2000»
13 years 7 months ago
A Single-Chip Multiprocessor for Smart Terminals
dards, language abstraction continues unabatrpretation of such high-level abstract languages requires high performance. The MP98 low-power, high-performance microprocessor architec...
Masato Edahiro, Satoshi Matsushita, Masakazu Yamas...
MICRO
2000
IEEE
122views Hardware» more  MICRO 2000»
13 years 7 months ago
An Integrated Environment for Teaching Computer Architecture
Jovan Djordjevic, Aleksandar Milenkovic, Nenad Grb...
MICRO
2000
IEEE
129views Hardware» more  MICRO 2000»
13 years 7 months ago
Architectural Considerations for CPU and Network Interface Integration
The popularity of the Internet and the emergence of broadband access networks is fueling the development of communications processors -- devices that integrate processing, network...
Charles D. Cranor, R. Gopalakrishnan, Peter Z. Onu...
MICRO
2000
IEEE
88views Hardware» more  MICRO 2000»
13 years 7 months ago
Two-level hierarchical register file organization for VLIW processors
High-performance microprocessors are currently designed to exploit the inherent instruction level parallelism (ILP) available in most applications. The techniques used in their de...
Javier Zalamea, Josep Llosa, Eduard Ayguadé...
MICRO
2000
IEEE
107views Hardware» more  MICRO 2000»
13 years 7 months ago
An integrated approach to accelerate data and predicate computations in hyperblocks
To exploit increased instruction-level parallelism available in modern processors, we describe the formation and optimization of tracenets, an integrated approach to reducing the ...
Alexandre E. Eichenberger, Waleed Meleis, Suman Ma...
MICRO
2000
IEEE
72views Hardware» more  MICRO 2000»
13 years 7 months ago
PipeRench implementation of the instruction path coprocessor
This paper demonstrates how an Instruction Path Coprocessor (I-COP) can be efficiently implemented using the PipeRench reconfigurable architecture. An I-COP is a programmable on-c...
Yuan C. Chou, Pazhani Pillai, Herman Schmit, John ...
ETS
2007
IEEE
76views Hardware» more  ETS 2007»
13 years 7 months ago
A Method of Cross-level Frequent Pattern Mining for Web-based Instruction
Yueh-Min Huang, Juei-Nan Chen, Shu-Chen Cheng
ETS
2002
IEEE
78views Hardware» more  ETS 2002»
13 years 7 months ago
Technology in Organizational Learning: Using High Tech for High Touch
This study describes the use of technology to enhance an experiential adult learning process, which occurred in a participatory organizational climate assessment. In this case, co...
Jane B. Maestro-Scherer, Robert E. Rich, Clifford ...