Sciweavers

DSD
2010
IEEE
153views Hardware» more  DSD 2010»
13 years 8 months ago
Simulation of High-Performance Memory Allocators
—Current general-purpose memory allocators do not provide sufficient speed or flexibility for modern highperformance applications. To optimize metrics like performance, memory us...
José Luis Risco-Martín, José ...
DSD
2010
IEEE
126views Hardware» more  DSD 2010»
13 years 8 months ago
Low Power FPGA Implementations of 256-bit Luffa Hash Function
Low power techniques in a FPGA implementation of the hash function called Luffa are presented in this paper. This hash function is under consideration for adoption as standard. Tw...
Paris Kitsos, Nicolas Sklavos, Athanassios N. Skod...
DSD
2010
IEEE
140views Hardware» more  DSD 2010»
13 years 8 months ago
RobuCheck: A Robustness Checker for Digital Circuits
Abstract—Continuously shrinking feature sizes cause an increasing vulnerability of digital circuits. Manufacturing failures and transient faults may tamper the functionality. Aut...
Stefan Frehse, Görschwin Fey, André S&...
DSD
2010
IEEE
190views Hardware» more  DSD 2010»
13 years 8 months ago
Hardware-Based Speed Up of Face Recognition Towards Real-Time Performance
— Real-time face recognition by computer systems is required in many commercial and security applications because it is the only way to protect privacy and security in the sea of...
I. Sajid, Sotirios G. Ziavras, M. M. Ahmed
DSD
2010
IEEE
99views Hardware» more  DSD 2010»
13 years 8 months ago
Trading Hardware Overhead for Communication Performance in Mesh-Type Topologies
—Several alternatives of mesh-type topologies have been published for the use in Networks-on-Chip. Due to their regularity, mesh-type topologies often serve as a foundation to in...
Claas Cornelius, Philipp Gorski, Stephan Kubisch, ...
DSD
2010
IEEE
172views Hardware» more  DSD 2010»
13 years 8 months ago
Adaptive Cache Memories for SMT Processors
Abstract—Resizable caches can trade-off capacity for access speed to dynamically match the needs of the workload. In Simultaneous Multi-Threaded (SMT) cores, the caching needs ca...
Sonia López, Oscar Garnica, David H. Albone...
DATE
2010
IEEE
142views Hardware» more  DATE 2010»
13 years 8 months ago
Transition-aware real-time task scheduling for reconfigurable embedded systems
—Due to increase in demand for reconfigurability in embedded systems, real-time task scheduling is challenged by non-negligible reconfiguration overheads. If such overheads are n...
Hessam Kooti, Elaheh Bozorgzadeh, Shenghui Liao, L...
DATE
2010
IEEE
146views Hardware» more  DATE 2010»
13 years 8 months ago
Automatic pipelining from transactional datapath specifications
Abstract—We present a transactional datapath specification (Tspec) and the tool (T-piper) to synthesize automatically an inpelined implementation from it. T-spec abstractly views...
Eriko Nurvitadhi, James C. Hoe, Timothy Kam, Shih-...
DATE
2010
IEEE
119views Hardware» more  DATE 2010»
13 years 8 months ago
Practical Monte-Carlo based timing yield estimation of digital circuits
—The advanced sampling and variance reduction techniques as efficient alternatives to the slow crude-MC method have recently been adopted for the analysis of timing yield in dig...
Javid Jaffari, Mohab Anis
CAV
2010
Springer
156views Hardware» more  CAV 2010»
13 years 8 months ago
A Logical Product Approach to Zonotope Intersection
We define and study a new abstract domain which is a fine-grained combination of zonotopes with (sub-)polyhedric domains such as the interval, ocinear template or polyhedron domain...
Khalil Ghorbal, Eric Goubault, Sylvie Putot