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DATE
2005
IEEE
143views Hardware» more  DATE 2005»
13 years 10 months ago
Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies
Operating frequency of a pipelined circuit is determined by the delay of the slowest pipeline stage. However, under statistical delay variation in sub-100nm technology regime, the...
Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay,...
DATE
2005
IEEE
131views Hardware» more  DATE 2005»
13 years 10 months ago
Performance Driven Decoupling Capacitor Allocation Considering Data and Clock Interactions
— We propose a sensitivity-based method to allocate decaps incorporating leakage constraints and tighter data and clock interactions. The proposed approach attempts to allocate d...
Ajith Chandy, Tom Chen
DATE
2005
IEEE
100views Hardware» more  DATE 2005»
13 years 10 months ago
The Role of Model-Level Transactors and UML in Functional Prototyping of Systems-on-Chip: A Software-Radio Application
Developing a functional prototype of a system-on-chip provides a unifying vehicle for model validation and system refinement. Keeping the prototype executable everal abstraction l...
Alexandre Chureau, Yvon Savaria, El Mostapha Aboul...
DATE
2005
IEEE
133views Hardware» more  DATE 2005»
13 years 10 months ago
A Real-Time Streaming Memory Controller
Artur Burchard, Ewa Hekstra-Nowacka, Atul Chauhan
DATE
2005
IEEE
94views Hardware» more  DATE 2005»
13 years 10 months ago
A New Approach to Component Testing
Carefully tested electric/electronic components are a requirement for effective hardware-in-the-loop tests and vehicle tests in automotive industry. A new method for definition an...
Horst Brinkmeyer
DSD
2006
IEEE
113views Hardware» more  DSD 2006»
13 years 10 months ago
Cascade Scheme for Concurrent Errors Detection
The paper deals with synthesis technique for designing circuits with cascade errors detection. The proposed technique is based on partitioning a scheme into a number of cascades f...
Ilya Levin, Vladimir Ostrovsky, Osnat Keren, Vladi...
ISQED
2010
IEEE
126views Hardware» more  ISQED 2010»
13 years 10 months ago
Modeling and verification of industrial flash memories
We present a method to abstract, formalize, and verify industrial flash memory implementations. Flash memories contain specialized transistors, e.g., floating gate and split gate d...
Sandip Ray, Jayanta Bhadra, Thomas Portlock, Ronal...
ISARCS
2010
156views Hardware» more  ISARCS 2010»
13 years 10 months ago
A Road to a Formally Verified General-Purpose Operating System
Methods of formal description and verification represent a viable way for achieving fundamentally bug-free software. However, in reality only a small subset of the existing operati...
Martin Decký
CHARME
2005
Springer
145views Hardware» more  CHARME 2005»
13 years 10 months ago
Maximal Input Reduction of Sequential Netlists via Synergistic Reparameterization and Localization Strategies
Abstract. Automatic formal verification techniques generally require exponential resources with respect to the number of primary inputs of a netlist. In this paper, we present sev...
Jason Baumgartner, Hari Mony
ATVA
2006
Springer
109views Hardware» more  ATVA 2006»
13 years 10 months ago
Proactive Leader Election in Asynchronous Shared Memory Systems
Abstract. In this paper, we give an algorithm for fault-tolerant proactive leader election in asynchronous shared memory systems, and later its formal verification. Roughly speakin...
M. C. Dharmadeep, K. Gopinath