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ISCA
1995
IEEE
92views Hardware» more  ISCA 1995»
14 years 5 days ago
A Comparison of Full and Partial Predicated Execution Support for ILP Processors
One can e ectively utilize predicated execution to improve branch handling in instruction-level parallel processors. Although the potential bene ts of predicated execution are hig...
Scott A. Mahlke, Richard E. Hank, James E. McCormi...
ISCA
1995
IEEE
118views Hardware» more  ISCA 1995»
14 years 5 days ago
The EM-X Parallel Computer: Architecture and Basic Performance
Latency tolerance is essential in achieving high performance on parallel computers for remote function calls and fine-grained remote memory accesses. EM-X supports interprocessor ...
Yuetsu Kodama, Hirohumi Sakane, Mitsuhisa Sato, Ha...
ISCA
1995
IEEE
133views Hardware» more  ISCA 1995»
14 years 5 days ago
Performance Evaluation of the PowerPC 620 Microarchitecture
The PowerPC 620TM microprocessor1 is the most recent and performance leading member of the PowerPCTM family. The 64-bit PowerPC 620 microprocessor employs a two-phase branch predi...
Trung A. Diep, Christopher Nelson, John Paul Shen
ISCA
1995
IEEE
109views Hardware» more  ISCA 1995»
14 years 5 days ago
Next Cache Line and Set Prediction
Accurate instruction fetch and branch prediction is increasingly important on today’s wide-issue architectures. Fetch prediction is the process of determining the next instructi...
Brad Calder, Dirk Grunwald
ISCA
1995
IEEE
110views Hardware» more  ISCA 1995»
14 years 5 days ago
Optimization of Instruction Fetch Mechanisms for High Issue Rates
Recent superscalar processors issue four instructions per cycle. These processors are also powered by highly-parallel superscalar cores. The potential performance can only be expl...
Thomas M. Conte, Kishore N. Menezes, Patrick M. Mi...
ISCA
1995
IEEE
120views Hardware» more  ISCA 1995»
14 years 5 days ago
Streamlining Data Cache Access with Fast Address Calculation
For many programs, especially integer codes, untolerated load instruction latencies account for a significant portion of total execution time. In this paper, we present the desig...
Todd M. Austin, Dionisios N. Pnevmatikatos, Gurind...
ISCA
1995
IEEE
120views Hardware» more  ISCA 1995»
14 years 5 days ago
Unconstrained Speculative Execution with Predicated State Buffering
Speculative execution is execution of instructions before it is known whether these instructions should be executed. Compiler-based speculative execution has the potential to achi...
Hideki Ando, Chikako Nakanishi, Tetsuya Hara, Masa...
MICRO
1997
IEEE
90views Hardware» more  MICRO 1997»
14 years 5 days ago
ProfileMe: Hardware Support for Instruction-Level Profiling on Out-of-Order Processors
Profile data is valuable for identifying performance bottlenecks and guiding optimizations. Periodic sampling of a processor's performance monitoring hardware is an effective...
Jeffrey Dean, James E. Hicks, Carl A. Waldspurger,...
ICES
1995
Springer
83views Hardware» more  ICES 1995»
14 years 5 days ago
Evolutionary Algorithms
Marco Tomassini
ICECCS
1995
IEEE
80views Hardware» more  ICECCS 1995»
14 years 5 days ago
Ensuring the satisfaction of a temporal specification at run-time
Grace Tsai, M. Insall, Bruce M. McMillin