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ISCA
1997
IEEE
119views Hardware» more  ISCA 1997»
14 years 5 days ago
The Agree Predictor: A Mechanism for Reducing Negative Branch History Interference
Deeply pipelined, superscalar processors require accurate branch prediction to achieve high performance. Two-level branch predictors have been shown to achieve high prediction acc...
Eric Sprangle, Robert S. Chappell, Mitch Alsup, Ya...
ISCA
1997
IEEE
78views Hardware» more  ISCA 1997»
14 years 5 days ago
Trading Conflict and Capacity Aliasing in Conditional Branch Predictors
As modern microprocessors employ deeper pipelines and issue multiple instructions per cycle, they are becoming increasingly dependent on accurate branch prediction. Because hardwa...
Pierre Michaud, André Seznec, Richard Uhlig
ISCA
1997
IEEE
93views Hardware» more  ISCA 1997»
14 years 5 days ago
The Energy Efficiency of IRAM Architectures
Portable systems demand energy efficiency in order to maximize battery life. IRAM architectures, which combine DRAM and a processor on the same chip in a DRAM process, are more en...
Richard Fromm, Stylianos Perissakis, Neal Cardwell...
ISCA
1997
IEEE
98views Hardware» more  ISCA 1997»
14 years 5 days ago
Target Prediction for Indirect Jumps
As the issue rate and pipeline depth of high performance superscalar processors increase, the amount of speculative work issued also increases. Because speculative work must be th...
Po-Yung Chang, Eric Hao, Yale N. Patt
ICCD
1995
IEEE
95views Hardware» more  ICCD 1995»
14 years 5 days ago
Caching processor general registers
Robert Yung, Neil C. Wilhelm
ICCD
1995
IEEE
85views Hardware» more  ICCD 1995»
14 years 5 days ago
A high-performance asynchronous SCSI controller
We describe thedesign of a high performance asynchronous SCSI Small Computer Systems Interface controller data path and the associated control circuits. The data path is an asyn...
Kenneth Y. Yun, David L. Dill
ICCD
1995
IEEE
100views Hardware» more  ICCD 1995»
14 years 5 days ago
Transformation of min-max optimization to least-square estimation and application to interconnect design optimization
This paper describes a novel approach to nd a tighter bound of the transformation of the Min-Max problems into the one of Least-Square Estimation. It is well known that the above ...
Jimmy Shinn-Hwa Wang, Wayne Wei-Ming Dai
ICCD
1995
IEEE
100views Hardware» more  ICCD 1995»
14 years 5 days ago
A coprocessor for accurate and reliable numerical computations
Michael J. Schulte, Earl E. Swartzlander Jr.
ICCD
1995
IEEE
121views Hardware» more  ICCD 1995»
14 years 5 days ago
Analysis of conditional resource sharing using a guard-based control representation
Optimization of hardware resources for conditional data-flow graph behavior is particularly important when conditional behavior occurs in cyclic loops and maximization of through...
Ivan P. Radivojevic, Forrest Brewer
ICCD
1995
IEEE
119views Hardware» more  ICCD 1995»
14 years 5 days ago
Extraction of finite state machines from transistor netlists by symbolic simulation
– This paper describes a new technique for extracting clock-level finite state machines(FSMs) from transistor netlists using symbolic simulation. The transistor netlist is prepr...
Manish Pandey, Alok Jain, Randal E. Bryant, Derek ...